drm/i915/psr: Add helper to get min psr guardband

Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.

This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.

v2:
- Account for flag `req_psr2_sdp_prior_scanline` and scl lines while
  computing min guardband. (Jouni)
- Use wake lines only for eDP with panel_replay and sel_update flags
  set. (Jouni)

Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20251017123504.2247954-2-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3e99a65ec98863991171c904b8bebfe7f35767b9..9c7364d6d69d22878e6ba08fb540e771dec016d9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4499,3 +4499,30 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 
        intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
 }
+
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       int psr_min_guardband;
+       int wake_lines;
+
+       if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+               return 0;
+
+       if (crtc_state->has_panel_replay)
+               wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+       else if (crtc_state->has_sel_update)
+               wake_lines = DISPLAY_VER(display) < 20 ?
+                            psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+                                                   crtc_state->alpm_state.fast_wake_lines) :
+                            crtc_state->alpm_state.io_wake_lines;
+       else
+               return 0;
+
+       psr_min_guardband = wake_lines + crtc_state->set_context_latency;
+
+       if (crtc_state->req_psr2_sdp_prior_scanline)
+               psr_min_guardband++;
+
+       return psr_min_guardband;
+}

diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index b17ce312dc3750c6e16d490de2f8994d739921a4..620b359288326caf0133f7013be68975b601a2f5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
                                   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
                                   struct intel_crtc_state *crtc_state);
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */