dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC

Add the device tree bindings for the display clock controller which are
required on Qualcomm Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com
[bjorn: Dropped unnecessary include in DT example]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml
new file mode 100644 (file)
index 0000000..45f027c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller on GLYMUR
+
+maintainers:
+  - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+  Qualcomm display clock control module which supports the clocks, resets and
+  power domains for the MDSS instances on GLYMUR SoC.
+
+  See also:
+    include/dt-bindings/clock/qcom,dispcc-glymur.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,glymur-dispcc
+
+  clocks:
+    items:
+      - description: Board CXO clock
+      - description: Board sleep clock
+      - description: DisplayPort 0 link clock
+      - description: DisplayPort 0 VCO div clock
+      - description: DisplayPort 1 link clock
+      - description: DisplayPort 1 VCO div clock
+      - description: DisplayPort 2 link clock
+      - description: DisplayPort 2 VCO div clock
+      - description: DisplayPort 3 link clock
+      - description: DisplayPort 3 VCO div clock
+      - description: DSI 0 PLL byte clock
+      - description: DSI 0 PLL DSI clock
+      - description: DSI 1 PLL byte clock
+      - description: DSI 1 PLL DSI clock
+      - description: Standalone PHY 0 PLL link clock
+      - description: Standalone PHY 0 VCO div clock
+      - description: Standalone PHY 1 PLL link clock
+      - description: Standalone PHY 1 VCO div clock
+
+  power-domains:
+    description:
+      A phandle and PM domain specifier for the MMCX power domain.
+    maxItems: 1
+
+  required-opps:
+    description:
+      A phandle to an OPP node describing required MMCX performance point.
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    clock-controller@af00000 {
+      compatible = "qcom,glymur-dispcc";
+      reg = <0x0af00000 0x20000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>,
+               <&mdss_dp_phy0 0>,
+               <&mdss_dp_phy0 1>,
+               <&mdss_dp_phy1 0>,
+               <&mdss_dp_phy1 1>,
+               <&mdss_dp_phy2 0>,
+               <&mdss_dp_phy2 1>,
+               <&mdss_dp_phy3 0>,
+               <&mdss_dp_phy3 1>,
+               <&mdss_dsi0_phy 0>,
+               <&mdss_dsi0_phy 1>,
+               <&mdss_dsi1_phy 0>,
+               <&mdss_dsi1_phy 1>,
+               <&mdss_phy0_link 0>,
+               <&mdss_phy0_vco_div 0>,
+               <&mdss_phy1_link 1>,
+               <&mdss_phy1_vco_div 1>;
+      power-domains = <&rpmhpd RPMHPD_MMCX>;
+      required-opps = <&rpmhpd_opp_low_svs>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,glymur-dispcc.h b/include/dt-bindings/clock/qcom,glymur-dispcc.h
new file mode 100644 (file)
index 0000000..a845d76
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-dispcc.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK                                     0
+#define DISP_CC_ESYNC0_CLK_SRC                                 1
+#define DISP_CC_ESYNC1_CLK                                     2
+#define DISP_CC_ESYNC1_CLK_SRC                                 3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK                            4
+#define DISP_CC_MDSS_AHB1_CLK                                  5
+#define DISP_CC_MDSS_AHB_CLK                                   6
+#define DISP_CC_MDSS_AHB_CLK_SRC                               7
+#define DISP_CC_MDSS_BYTE0_CLK                                 8
+#define DISP_CC_MDSS_BYTE0_CLK_SRC                             9
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                         10
+#define DISP_CC_MDSS_BYTE0_INTF_CLK                            11
+#define DISP_CC_MDSS_BYTE1_CLK                                 12
+#define DISP_CC_MDSS_BYTE1_CLK_SRC                             13
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC                         14
+#define DISP_CC_MDSS_BYTE1_INTF_CLK                            15
+#define DISP_CC_MDSS_DPTX0_AUX_CLK                             16
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC                         17
+#define DISP_CC_MDSS_DPTX0_LINK_CLK                            18
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC                                19
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC                    20
+#define DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK                       21
+#define DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC               22
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK                       23
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK                          24
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC                      25
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK                          26
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC                      27
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK            28
+#define DISP_CC_MDSS_DPTX1_AUX_CLK                             29
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC                         30
+#define DISP_CC_MDSS_DPTX1_LINK_CLK                            31
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC                                32
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC                    33
+#define DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK                       34
+#define DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC               35
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK                       36
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK                          37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC                      38
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK                          39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC                      40
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK            41
+#define DISP_CC_MDSS_DPTX2_AUX_CLK                             42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC                         43
+#define DISP_CC_MDSS_DPTX2_LINK_CLK                            44
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC                                45
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC                    46
+#define DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK                       47
+#define DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC               48
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK                       49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK                          50
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC                      51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK                          52
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC                      53
+#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK            54
+#define DISP_CC_MDSS_DPTX3_AUX_CLK                             55
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC                         56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK                            57
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC                                58
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC                    59
+#define DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK                       60
+#define DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC               61
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK                       62
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK                          63
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC                      64
+#define DISP_CC_MDSS_ESC0_CLK                                  65
+#define DISP_CC_MDSS_ESC0_CLK_SRC                              66
+#define DISP_CC_MDSS_ESC1_CLK                                  67
+#define DISP_CC_MDSS_ESC1_CLK_SRC                              68
+#define DISP_CC_MDSS_MDP1_CLK                                  69
+#define DISP_CC_MDSS_MDP_CLK                                   70
+#define DISP_CC_MDSS_MDP_CLK_SRC                               71
+#define DISP_CC_MDSS_MDP_LUT1_CLK                              72
+#define DISP_CC_MDSS_MDP_LUT_CLK                               73
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK                          74
+#define DISP_CC_MDSS_PCLK0_CLK                                 75
+#define DISP_CC_MDSS_PCLK0_CLK_SRC                             76
+#define DISP_CC_MDSS_PCLK1_CLK                                 77
+#define DISP_CC_MDSS_PCLK1_CLK_SRC                             78
+#define DISP_CC_MDSS_PCLK2_CLK                                 79
+#define DISP_CC_MDSS_PCLK2_CLK_SRC                             80
+#define DISP_CC_MDSS_RSCC_AHB_CLK                              81
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK                            82
+#define DISP_CC_MDSS_VSYNC1_CLK                                        83
+#define DISP_CC_MDSS_VSYNC_CLK                                 84
+#define DISP_CC_MDSS_VSYNC_CLK_SRC                             85
+#define DISP_CC_OSC_CLK                                                86
+#define DISP_CC_OSC_CLK_SRC                                    87
+#define DISP_CC_PLL0                                           88
+#define DISP_CC_PLL1                                           89
+#define DISP_CC_SLEEP_CLK                                      90
+#define DISP_CC_SLEEP_CLK_SRC                                  91
+#define DISP_CC_XO_CLK                                         92
+#define DISP_CC_XO_CLK_SRC                                     93
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC                                 0
+#define DISP_CC_MDSS_CORE_INT2_GDSC                            1
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR                                  0
+#define DISP_CC_MDSS_CORE_INT2_BCR                             1
+#define DISP_CC_MDSS_RSCC_BCR                                  2
+
+#endif