ARM64: zynqmp: List all i2c muxes as separate buses for ZCU102

Simplify work with I2C muxes by definitely i2c bus topology.
Here is example of it:
ZynqMP> i2c bus
Bus 0:	zynq_0
Bus 1:	zynq_0->PCA9544A@0x75:0
Bus 2:	zynq_0->PCA9544A@0x75:1
Bus 3:	zynq_0->PCA9544A@0x75:2
Bus 4:	zynq_1
Bus 5:	zynq_1->PCA9548@0x74:0
Bus 6:	zynq_1->PCA9548@0x74:1
Bus 7:	zynq_1->PCA9548@0x74:2
Bus 8:	zynq_1->PCA9548@0x74:3
Bus 9:	zynq_1->PCA9548@0x74:4
Bus 10:	zynq_1->PCA9548@0x75:0
Bus 11:	zynq_1->PCA9548@0x75:1
Bus 12:	zynq_1->PCA9548@0x75:2
Bus 13:	zynq_1->PCA9548@0x75:3
Bus 14:	zynq_1->PCA9548@0x75:4
Bus 15:	zynq_1->PCA9548@0x75:5
Bus 16:	zynq_1->PCA9548@0x75:6
Bus 17:	zynq_1->PCA9548@0x75:7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index ce9d6e0242e133677fac2196637621b1b6862671..cd14bc4d6c7bd9db564d8c73c3a2582a3dfb7994 100644 (file)
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -18,6 +18,29 @@
 #define CONFIG_ZYNQ_SDHCI1
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_MAX_HOPS                1
+#define CONFIG_SYS_NUM_I2C_BUSES       18
+#define CONFIG_SYS_I2C_BUSES   { \
+                               {0, {I2C_NULL_HOP} }, \
+                               {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+                               {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+                               {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+                               {1, {I2C_NULL_HOP} }, \
+                               {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+                               {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+                               }
+
 #define CONFIG_SYS_I2C_ZYNQ
 #define CONFIG_AHCI