ARM: xilinx: Add support for UltraScale MP

Basic support for new Xilinx UltraScale MP soc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/ultrascale/Makefile b/arch/arm/cpu/armv8/ultrascale/Makefile
new file mode 100644 (file)
index 0000000..831d025
--- /dev/null
+++ b/arch/arm/cpu/armv8/ultrascale/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += clk.o

diff --git a/arch/arm/cpu/armv8/ultrascale/clk.c b/arch/arm/cpu/armv8/ultrascale/clk.c
new file mode 100644 (file)
index 0000000..41fb60e
--- /dev/null
+++ b/arch/arm/cpu/armv8/ultrascale/clk.c
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+unsigned long get_uart_clk(int dev_id)
+{
+       return 25000000;
+}

diff --git a/arch/arm/include/asm/arch-ultrascale/clk.h b/arch/arm/include/asm/arch-ultrascale/clk.h
new file mode 100644 (file)
index 0000000..9f18ea9
--- /dev/null
+++ b/arch/arm/include/asm/arch-ultrascale/clk.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLK_H_
+#define _ASM_ARCH_CLK_H_
+
+unsigned long get_uart_clk(int dev_id);
+
+#endif /* _ASM_ARCH_CLK_H_ */

diff --git a/arch/arm/include/asm/arch-ultrascale/hardware.h b/arch/arm/include/asm/arch-ultrascale/hardware.h
new file mode 100644 (file)
index 0000000..7893e86
--- /dev/null
+++ b/arch/arm/include/asm/arch-ultrascale/hardware.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE      0xFD3FF000
+#define GICC_BASE      0xFD3FE100
+
+#define ZYNQ_SERIAL_BASEADDR0  0xFF000000
+#define ZYNQ_SERIAL_BASEADDR1  0xFF001000
+
+#endif /* _ASM_ARCH_HARDWARE_H */

diff --git a/board/xilinx/ultrascale/Makefile b/board/xilinx/ultrascale/Makefile
new file mode 100644 (file)
index 0000000..60fb2ef
--- /dev/null
+++ b/board/xilinx/ultrascale/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := ultrascale.o

diff --git a/board/xilinx/ultrascale/ultrascale.c b/board/xilinx/ultrascale/ultrascale.c
new file mode 100644 (file)
index 0000000..e1264ef
--- /dev/null
+++ b/board/xilinx/ultrascale/ultrascale.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int timer_init(void)
+{
+       return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}

diff --git a/boards.cfg b/boards.cfg
index a32f46bc4e45ca1d4e86a0e622ec9e7be65920f8..9164a0baf9f2143e69c1430a0210faaf0b7909b8 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,6 +44,7 @@
 ###########################################################################################################
 
 Active  aarch64     armv8          -           armltd          vexpress64          vexpress_aemv8a                      vexpress_aemv8a:ARM64                                                                                                             David Feng <fenghua@phytium.com.cn>
+Active  aarch64     armv8          ultrascale  xilinx          ultrascale          xilinx_ultrascale                    xilinx_ultrascale:ARM64                                                                                                           Michal Simek <michal.simek@xilinx.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4-be                         -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/include/configs/xilinx_ultrascale.h b/include/configs/xilinx_ultrascale.h
new file mode 100644 (file)
index 0000000..b1bc7b8
--- /dev/null
+++ b/include/configs/xilinx_ultrascale.h
@@ -0,0 +1,98 @@
+/*
+ * Configuration for Xilinx UltraScale MP
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __XILINX_ULTRASCALE_H
+#define __XILINX_ULTRASCALE_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_REMAKE_ELF
+
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+#define CONFIG_SYS_NO_FLASH
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_SYS_SDRAM_SIZE          0x40000000
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x40000000
+
+/* Have release address at the end of 256MB for now */
+#define CPU_RELEASE_ADDR       0xFFFFFF0
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_IDENT_STRING            " Xilinx UltraScale MP"
+#define CONFIG_BOOTP_VCI_STRING                "U-boot.armv8.Xilinx_UltraScale_MP"
+
+/* Text base on 16MB for now - 0 doesn't work */
+#define CONFIG_SYS_TEXT_BASE           0x100000
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_DEFAULT_DEVICE_TREE     ultrascale
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY              0x1800000 /* 24MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+
+/* Serial setup */
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_SERIAL
+
+#define CONFIG_CONS_INDEX              0
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR           0x8000000
+
+/* Initial environment variables */
+#define CONFIG_BOOTARGS                        "console=ttyPS0"
+#define CONFIG_BOOTCOMMAND             "echo Hello Xilinx UltraScale MP"
+#define CONFIG_BOOTDELAY               -1
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE          1
+#define CONFIG_ENV_SIZE                        0x1000
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              512     
+#define CONFIG_SYS_PROMPT              "UltraScale> "
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING         1
+/* max command args */
+#define CONFIG_SYS_MAXARGS             64
+
+#endif /* __XILINX_ULTRASCALE_H */