x86,fs/resctrl: Detect io_alloc feature

AMD's SDCIAE (SDCI Allocation Enforcement) PQE feature enables system software
to control the portions of L3 cache used for direct insertion of data from I/O
devices into the L3 cache.

Introduce a generic resctrl cache resource property "io_alloc_capable" as the
first part of the new "io_alloc" resctrl feature that will support AMD's
SDCIAE. Any architecture can set a cache resource as "io_alloc_capable" if
a portion of the cache can be allocated for I/O traffic.

Set the "io_alloc_capable" property for the L3 cache resource on x86 (AMD)
systems that support SDCIAE.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/df85a9a6081674fd3ef6b4170920485512ce2ded.1762995456.git.babu.moger@amd.com

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 2b2935b3df8d302175b3fbc3c193907df7ac4224..3792ab4819dc62e10e46aaf9cbcfb4e397093976 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -274,6 +274,11 @@ static void rdt_get_cdp_config(int level)
        rdt_resources_all[level].r_resctrl.cdp_capable = true;
 }
 
+static void rdt_set_io_alloc_capable(struct rdt_resource *r)
+{
+       r->cache.io_alloc_capable = true;
+}
+
 static void rdt_get_cdp_l3_config(void)
 {
        rdt_get_cdp_config(RDT_RESOURCE_L3);
@@ -855,6 +860,8 @@ static __init bool get_rdt_alloc_resources(void)
                rdt_get_cache_alloc_cfg(1, r);
                if (rdt_cpu_has(X86_FEATURE_CDP_L3))
                        rdt_get_cdp_l3_config();
+               if (rdt_cpu_has(X86_FEATURE_SDCIAE))
+                       rdt_set_io_alloc_capable(r);
                ret = true;
        }
        if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {

diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
index a7d92718b653f51735e2fbb01ba9506e22e59a64..533f240dbe21eb9fcb7c5be3520bd222501b712b 100644 (file)
--- a/include/linux/resctrl.h
+++ b/include/linux/resctrl.h
@@ -206,6 +206,8 @@ struct rdt_mon_domain {
  * @arch_has_sparse_bitmasks:  True if a bitmask like f00f is valid.
  * @arch_has_per_cpu_cfg:      True if QOS_CFG register for this cache
  *                             level has CPU scope.
+ * @io_alloc_capable:  True if portion of the cache can be configured
+ *                     for I/O traffic.
  */
 struct resctrl_cache {
        unsigned int    cbm_len;
@@ -213,6 +215,7 @@ struct resctrl_cache {
        unsigned int    shareable_bits;
        bool            arch_has_sparse_bitmasks;
        bool            arch_has_per_cpu_cfg;
+       bool            io_alloc_capable;
 };
 
 /**