--- /dev/null
+From ab1e85372168892387dd1ac171158fc8c3119be4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Fri, 14 Nov 2014 21:43:33 +0100
+Subject: ARM: mvebu: fix ordering in Armada 370 .dtsi
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+
+commit ab1e85372168892387dd1ac171158fc8c3119be4 upstream.
+
+Commit a095b1c78a35 ("ARM: mvebu: sort DT nodes by address")
+missed placing the system-controller in the correct order.
+
+Fixes: a095b1c78a35 ("ARM: mvebu: sort DT nodes by address")
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lkml.kernel.org/r/20141114204333.GS27002@pengutronix.de
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/armada-370.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-370.dtsi
++++ b/arch/arm/boot/dts/armada-370.dtsi
+@@ -106,11 +106,6 @@
+ reg = <0x11100 0x20>;
+ };
+
+- system-controller@18200 {
+- compatible = "marvell,armada-370-xp-system-controller";
+- reg = <0x18200 0x100>;
+- };
+-
+ pinctrl {
+ compatible = "marvell,mv88f6710-pinctrl";
+ reg = <0x18000 0x38>;
+@@ -167,6 +162,11 @@
+ interrupts = <91>;
+ };
+
++ system-controller@18200 {
++ compatible = "marvell,armada-370-xp-system-controller";
++ reg = <0x18200 0x100>;
++ };
++
+ gateclk: clock-gating-control@18220 {
+ compatible = "marvell,armada-370-gating-clock";
+ reg = <0x18220 0x4>;
--- /dev/null
+From e4a680099a6e97ecdbb81081cff9e4a489a4dc44 Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <digetx@gmail.com>
+Date: Fri, 10 Oct 2014 17:24:47 +0400
+Subject: ARM: tegra: Re-add removed SoC id macro to tegra_resume()
+
+From: Dmitry Osipenko <digetx@gmail.com>
+
+commit e4a680099a6e97ecdbb81081cff9e4a489a4dc44 upstream.
+
+Commit d127e9c ("ARM: tegra: make tegra_resume can work with current and later
+chips") removed tegra_get_soc_id macro leaving used cpu register corrupted after
+branching to v7_invalidate_l1() and as result causing execution of unintended
+code on tegra20. Possibly it was expected that r6 would be SoC id func argument
+since common cpu reset handler is setting r6 before branching to tegra_resume(),
+but neither tegra20_lp1_reset() nor tegra30_lp1_reset() aren't setting r6
+register before jumping to resume function. Fix it by re-adding macro.
+
+Fixes: d127e9c (ARM: tegra: make tegra_resume can work with current and later chips)
+Reviewed-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-tegra/reset-handler.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-tegra/reset-handler.S
++++ b/arch/arm/mach-tegra/reset-handler.S
+@@ -51,6 +51,7 @@ ENTRY(tegra_resume)
+ THUMB( it ne )
+ bne cpu_resume @ no
+
++ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+ /* Are we on Tegra20? */
+ cmp r6, #TEGRA20
+ beq 1f @ Yes
--- /dev/null
+From 7d57511d2dba03a8046c8b428dd9192a4bfc1e73 Mon Sep 17 00:00:00 2001
+From: Catalin Marinas <catalin.marinas@arm.com>
+Date: Mon, 17 Nov 2014 10:37:40 +0000
+Subject: arm64: Add COMPAT_HWCAP_LPAE
+
+From: Catalin Marinas <catalin.marinas@arm.com>
+
+commit 7d57511d2dba03a8046c8b428dd9192a4bfc1e73 upstream.
+
+Commit a469abd0f868 (ARM: elf: add new hwcap for identifying atomic
+ldrd/strd instructions) introduces HWCAP_ELF for 32-bit ARM
+applications. As LPAE is always present on arm64, report the
+corresponding compat HWCAP to user space.
+
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/include/asm/hwcap.h | 1 +
+ arch/arm64/kernel/setup.c | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/include/asm/hwcap.h
++++ b/arch/arm64/include/asm/hwcap.h
+@@ -30,6 +30,7 @@
+ #define COMPAT_HWCAP_IDIVA (1 << 17)
+ #define COMPAT_HWCAP_IDIVT (1 << 18)
+ #define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
++#define COMPAT_HWCAP_LPAE (1 << 20)
+ #define COMPAT_HWCAP_EVTSTRM (1 << 21)
+
+ #ifndef __ASSEMBLY__
+--- a/arch/arm64/kernel/setup.c
++++ b/arch/arm64/kernel/setup.c
+@@ -67,7 +67,8 @@ EXPORT_SYMBOL_GPL(elf_hwcap);
+ COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
+ COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
+ COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
+- COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
++ COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
++ COMPAT_HWCAP_LPAE)
+ unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
+ #endif
+
dm-space-map-metadata-fix-sm_bootstrap_get_nr_blocks.patch
dm-thin-fix-inability-to-discard-blocks-when-in-out-of-data-space-mode.patch
dm-thin-fix-missing-out-of-data-space-to-write-mode-transition-if-blocks-are-released.patch
+arm64-add-compat_hwcap_lpae.patch
+arm-tegra-re-add-removed-soc-id-macro-to-tegra_resume.patch
+arm-mvebu-fix-ordering-in-armada-370-.dtsi.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
