arm64: dts: axiado: Add AX3005 SCM3005 device tree

Add device tree source files for the Axiado AX3005 SCM3005 board.
The AX3005 is a quad-core 64-bit ARMv8 Cortex-A53 SoC.

The DTSI describes the SoC-level nodes: GIC-v3 interrupt controller,
Cadence/Zynq UART, fixed reference clock, and spin-table secondary
CPU boot.  A /memreserve/ directive protects the spin-table release
address at 0x80002fa0 from being overwritten during boot.

The SCM3005 DTS sets the console to uart3 at 115200 baud and declares
2 GB of DRAM starting at 0x80000000.

Tested-by: Siu Ming Tong <smtong@axiado.com>
Signed-off-by: Karthikeyan Mitran <kmitran@axiado.com>
Signed-off-by: Siu Ming Tong <smtong@axiado.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bff341d6118254b40bb246211154bfc836490c94..fcc62505987ed1db5a20b829ea775db57e5e3959 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
+dtb-$(CONFIG_TARGET_SCM3005) += ax3005-scm3005.dtb
 
 dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb

diff --git a/arch/arm/dts/ax3005-scm3005.dts b/arch/arm/dts/ax3005-scm3005.dts
new file mode 100644 (file)
index 0000000..b684602
--- /dev/null
+++ b/arch/arm/dts/ax3005-scm3005.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+/dts-v1/;
+
+#include "ax3005.dtsi"
+
+/ {
+       model = "Axiado AX3005 SCM3005";
+       compatible = "axiado,ax3005-scm3005", "axiado,ax3005";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       chosen {
+               stdout-path = "serial3:115200";
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x00 0x80000000 0x00 0x80000000>;
+       };
+};
+
+&uart3 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/ax3005.dtsi b/arch/arm/dts/ax3005.dtsi
new file mode 100644 (file)
index 0000000..6df2e4a
--- /dev/null
+++ b/arch/arm/dts/ax3005.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80002fa0 0x00000008;
+
+/ {
+       aliases {
+               serial3 = &uart3;
+       };
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x0>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x80002fa0>;
+               };
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x1>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x80002fa0>;
+               };
+               cpu2: cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x2>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x80002fa0>;
+               };
+               cpu3: cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x3>;
+                       enable-method = "spin-table";
+                       cpu-release-addr = <0x0 0x80002fa0>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupt-parent = <&gic500>;
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+               clock-frequency = <1000000000>;
+       };
+
+       clocks {
+               refclk: refclk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <125000000>;
+                       bootph-pre-reloc;
+               };
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               interrupt-parent = <&gic500>;
+               ranges;
+
+               gic500: interrupt-controller@40400000 {
+                       compatible = "arm,gic-v3";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       #redistributor-regions = <1>;
+                       reg = <0x00 0x40400000 0x00 0x10000>,
+                             <0x00 0x40500000 0x00 0xc0000>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               uart3: serial@33020800 {
+                       compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                       reg = <0x00 0x33020800 0x00 0x100>;
+                       clock-names = "uart_clk", "pclk";
+                       clocks = <&refclk &refclk>;
+                       bootph-pre-reloc;
+                       status = "disabled";
+               };
+       };
+};