]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amd/display: Align cursor cache address to 2KB
authorJoshua Aberback <joshua.aberback@amd.com>
Sat, 27 Feb 2021 00:44:24 +0000 (19:44 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 12 May 2021 06:39:45 +0000 (08:39 +0200)
[ Upstream commit 554ba183b135ef09250b61a202d88512b5bbd03a ]

[Why]
The registers for the address of the cursor are aligned to 2KB, so all
cursor surfaces also need to be aligned to 2KB. Currently, the
provided cursor cache surface is not aligned, so we need a workaround
until alignment is enforced by the surface provider.

[How]
 - round up surface address to nearest multiple of 2048
 - current policy is to provide a much bigger cache size than
   necessary,so this operation is safe

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

index 06dc1e2e8383acdb2bc8d3819e07e3df8dbf763e..07c8d2e2c09c257d191104f83b157bc59f30d970 100644 (file)
@@ -848,7 +848,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 
                                        cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
                                        cmd.mall.cursor_copy_dst.quad_part =
-                                                       plane->address.grph.cursor_cache_addr.quad_part;
+                                                       (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
                                        cmd.mall.cursor_width = cursor_attr.width;
                                        cmd.mall.cursor_height = cursor_attr.height;
                                        cmd.mall.cursor_pitch = cursor_attr.pitch;
@@ -858,8 +858,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
                                        dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 
                                        /* Use copied cursor, and it's okay to not switch back */
-                                       cursor_attr.address.quad_part =
-                                                       plane->address.grph.cursor_cache_addr.quad_part;
+                                       cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
                                        dc_stream_set_cursor_attributes(stream, &cursor_attr);
                                }