drm/i915: Compute per-crtc min_cdclk earlier

Currently we compute the min_cdclk for each pipe during
intel_cdclk_atomic_check(). But that is too late for the
pipe prefill vs. vblank length checks (done during
intel_compute_global_watermarks).

We can't just reorder these things due to other dependencies,
so instead pull only the per-crtc minimum cdclk calculation
ahead. We should have enough information for that as soon
as we've computed the min cdclk for the planes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251013201236.30084-8-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6c477b6a7b8ac816fde2ae41718ab86bca67948d..e92e7fd9fd13587897a77e564770dc08c857a6a2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2833,7 +2833,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
        return min_cdclk;
 }
 
-static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
+int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
        int min_cdclk;
 
@@ -3306,8 +3306,8 @@ static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state,
        for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
                                            new_crtc_state, i) {
                ret = intel_cdclk_update_crtc_min_cdclk(state, crtc,
-                                                       intel_crtc_compute_min_cdclk(old_crtc_state),
-                                                       intel_crtc_compute_min_cdclk(new_crtc_state),
+                                                       old_crtc_state->min_cdclk,
+                                                       new_crtc_state->min_cdclk,
                                                        need_cdclk_calc);
                if (ret)
                        return ret;
@@ -3527,7 +3527,7 @@ void intel_cdclk_update_hw_state(struct intel_display *display)
                if (crtc_state->hw.active)
                        cdclk_state->active_pipes |= BIT(pipe);
 
-               cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
+               cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;
                cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
        }
 

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 6b4cbb6d817bfa1b526542e58148da023be4ada0..1ff7d078b42c9f073f0c2fe6ffae7592e07d2d10 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -75,4 +75,6 @@ int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
                                      unsigned int prefill_lines_unadjusted,
                                      unsigned int prefill_lines_available);
 
+int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_CDCLK_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4367ecfab2b3bc7a8ec9a775150a5174cd5493db..bbb6ff929d6429154e193d267d8a5d44e8a2e0ef 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6449,6 +6449,9 @@ int intel_atomic_check(struct drm_device *dev,
        if (ret)
                goto fail;
 
+       for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+               new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state);
+
        ret = intel_compute_global_watermarks(state);
        if (ret)
                goto fail;

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f77d120733fd1779b41994bffa4472eb9755f461..203dd38a9ec46f17449aea48c6d8f97c490a8688 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1192,6 +1192,8 @@ struct intel_crtc_state {
 
        struct intel_crtc_wm_state wm;
 
+       int min_cdclk;
+
        int plane_min_cdclk[I915_MAX_PLANES];
 
        /* for packed/planar CbCr */

diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d5c432b613cef417e8cd19e633b2c6ca10163540..0dcb0597879a28102226c382b32ba344102ffe60 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -865,6 +865,11 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
                                    crtc_state->plane_min_cdclk[plane->id]);
                }
 
+               crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state);
+
+               drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",
+                           crtc->base.base.id, crtc->base.name, crtc_state->min_cdclk);
+
                intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
                                                 crtc_state->port_clock);
        }