re PR target/61423 (Incorrect conversion from unsigned int to floating point)

	PR target/61423
	* config/i386/i386.md (*floatunssi<mode>2_i387_with_xmm): New
	define_insn_and_split pattern, merged from *floatunssi<mode>2_1
	and corresponding splitters.  Zero extend general register
	or memory input operand to XMM temporary.  Enable for
	TARGET_SSE2 and TARGET_INTER_UNIT_MOVES_TO_VEC only.
	(floatunssi<mode>2): Update expander predicate.

testsuite/ChangeLog:

	PR target/61423
	* gcc.target/i386/pr61423.c: New test.

From-SVN: r211321

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 40845337c02c4b09253f394250351832c3d86d1f..d2642bc39d9f6077f6448b4cc16acb9752a2355e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2014-06-06  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/61423
+       * config/i386/i386.md (*floatunssi<mode>2_i387_with_xmm): New
+       define_insn_and_split pattern, merged from *floatunssi<mode>2_1
+       and corresponding splitters.  Zero extend general register
+       or memory input operand to XMM temporary.  Enable for
+       TARGET_SSE2 and TARGET_INTER_UNIT_MOVES_TO_VEC only.
+       (floatunssi<mode>2): Update expander predicate.
+
 2014-06-06  Vladimir Makarov  <vmakarov@redhat.com>
 
        PR rtl-optimization/61325
@@ -608,7 +618,7 @@
        vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
        Replace temporary __asm__ with __builtin_shuffle.
 
-2014-06-03  Andrew Bennett  <andrew.bennett@imgtec.com> 
+2014-06-03  Andrew Bennett  <andrew.bennett@imgtec.com>
 
        * config/mips/mips-cpus.def: Add mips32r3, mips32r5, mips64r3 and
        mips64r5.
@@ -619,8 +629,8 @@
        (ISA_MIPS32R5): New define.
        (ISA_MIPS64R3): New define.
        (ISA_MIPS64R5): New define.
-       (TARGET_CPU_CPP_BUILTINS): Added support for ISA_MIPS32R3, ISA_MIPS32R5,
-       ISA_MIPS64R3 and ISA_MIPS64R5.
+       (TARGET_CPU_CPP_BUILTINS): Added support for ISA_MIPS32R3,
+       ISA_MIPS32R5, ISA_MIPS64R3 and ISA_MIPS64R5.
        (MIPS_ISA_LEVEL_SPEC): Added support for mips32r3, mips32r5, mips64r3
        and mips64r5.
        (MIPS_ISA_SYNCI_SPEC): Likewise.
@@ -639,7 +649,7 @@
        * doc/invoke.texi: Document -mxpa and -mno-xpa MIPS command line
        options.
        * config/mips/mips.opt (mxpa): New option.
-       * config/mips/mips.h (ASM_SPEC): Pass mxpa and mno-xpa to the 
+       * config/mips/mips.h (ASM_SPEC): Pass mxpa and mno-xpa to the
        assembler.
 
 2014-06-03  Martin Jambor  <mjambor@suse.cz>
@@ -688,7 +698,7 @@
        * config/sh/constraints.md: Likewise EXTRA_CONSTRAINT.
 
 2014-06-02  Andrew Pinski  <apinski@cavium.com>
-    
+
        * config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER):
        /lib/ld-linux32-aarch64.so.1 is used for ILP32.
        (LINUX_TARGET_LINK_SPEC): Update linker script for ILP32.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index d08f47ee5d98e653a789a55589846af6e9b84ed8..228e3e8ab7b5996ab8f97625b79db3cc7c538524 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4943,66 +4943,37 @@
 
 ;; Avoid store forwarding (partial memory) stall penalty by extending
 ;; SImode value to DImode through XMM register instead of pushing two
-;; SImode values to stack. Note that even !TARGET_INTER_UNIT_MOVES_TO_VEC
-;; targets benefit from this optimization. Also note that fild
-;; loads from memory only.
+;; SImode values to stack. Also note that fild loads from memory only.
 
-(define_insn "*floatunssi<mode>2_1"
-  [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
+(define_insn_and_split "*floatunssi<mode>2_i387_with_xmm"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
        (unsigned_float:X87MODEF
-         (match_operand:SI 1 "nonimmediate_operand" "x,m")))
-   (clobber (match_operand:DI 2 "memory_operand" "=m,m"))
-   (clobber (match_scratch:SI 3 "=X,x"))]
+         (match_operand:SI 1 "nonimmediate_operand" "rm")))
+   (clobber (match_scratch:DI 3 "=x"))
+   (clobber (match_operand:DI 2 "memory_operand" "=m"))]
   "!TARGET_64BIT
    && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
-   && TARGET_SSE"
+   && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC"
   "#"
-  [(set_attr "type" "multi")
-   (set_attr "mode" "<MODE>")])
-
-(define_split
-  [(set (match_operand:X87MODEF 0 "register_operand")
-       (unsigned_float:X87MODEF
-         (match_operand:SI 1 "register_operand")))
-   (clobber (match_operand:DI 2 "memory_operand"))
-   (clobber (match_scratch:SI 3))]
-  "!TARGET_64BIT
-   && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
-   && TARGET_SSE
-   && reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0)
-       (float:X87MODEF (match_dup 2)))]
-  "operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);")
-
-(define_split
-  [(set (match_operand:X87MODEF 0 "register_operand")
-       (unsigned_float:X87MODEF
-         (match_operand:SI 1 "memory_operand")))
-   (clobber (match_operand:DI 2 "memory_operand"))
-   (clobber (match_scratch:SI 3))]
-  "!TARGET_64BIT
-   && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
-   && TARGET_SSE
-   && reload_completed"
-  [(set (match_dup 2) (match_dup 3))
+  "&& reload_completed"
+  [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
+   (set (match_dup 2) (match_dup 3))
    (set (match_dup 0)
        (float:X87MODEF (match_dup 2)))]
-{
-  emit_move_insn (operands[3], operands[1]);
-  operands[3] = simplify_gen_subreg (DImode, operands[3], SImode, 0);
-})
+  ""
+  [(set_attr "type" "multi")
+   (set_attr "mode" "<MODE>")])
 
 (define_expand "floatunssi<mode>2"
   [(parallel
      [(set (match_operand:X87MODEF 0 "register_operand")
           (unsigned_float:X87MODEF
             (match_operand:SI 1 "nonimmediate_operand")))
-      (clobber (match_dup 2))
-      (clobber (match_scratch:SI 3))])]
+      (clobber (match_scratch:DI 3))
+      (clobber (match_dup 2))])]
   "!TARGET_64BIT
    && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
-       && TARGET_SSE)
+       && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC)
        || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
 {
   if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9f97db486050547a857679cf266903a265df7b99..eba01f090aebbe7038981fe9bbe783f3a6fcfb82 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-06-06  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/61423
+       * gcc.target/i386/pr61423.c: New test.
+
 2014-06-06  Paolo Carlini  <paolo.carlini@oracle.com>
 
        PR c++/60184

diff --git a/gcc/testsuite/gcc.target/i386/pr61423.c b/gcc/testsuite/gcc.target/i386/pr61423.c
new file mode 100644 (file)
index 0000000..5b538a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr61423.c
@@ -0,0 +1,38 @@
+/* PR target/61423 */
+/* { dg-do run { target ia32 } } */
+/* { dg-options "-O1 -ftree-vectorize -msse2 -mfpmath=387 -mtune=core2" } */
+
+#define N 1024
+static unsigned int A[N];
+
+double
+__attribute__((noinline))
+func (void)
+{
+  unsigned int sum = 0;
+  unsigned i;
+  double t;
+
+  for (i = 0; i < N; i++)
+    sum += A[i];
+
+  t = sum;
+  return t;
+}
+
+int
+main ()
+{
+  unsigned i;
+  double d;
+
+  for(i = 0; i < N; i++)
+    A[i] = 1;
+
+  d = func();
+
+  if (d != 1024.0)
+    __builtin_abort ();
+
+  return 0;
+}