drm/amd/display: Extend inbox0 lock to run Replay/PSR

[Why]
The inbox1 infrastructure is deprecated, so to support display
power features requiring a DMUB interlock moving forward extend
the inbox0 locking conditions to also include Replay or PSR.

[How]
Implemented a series of changes to improve HW lock handling:
- Deprecated should_use_dmub_inbox1_lock() and guarded it with
  DCN401 flag.
- Migrated lock checks into inbox0 helpers and added PSR/Replay
  enablement checks to ensure correct behavior.
- Updated HWSS fast update path to acquire HW lock as needed
  using the new helpers.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Andrew Mazour <Andrew.Mazour@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index f95cb0cf4b8a626090e7dccd8eabd8be89490dcf..a7ec633b26c068141704cddf8b7d3cce3863a2b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -38,6 +38,7 @@
 #include "dccg.h"
 #include "abm.h"
 #include "dcn10/dcn10_hubbub.h"
+#include "dce/dmub_hw_lock_mgr.h"
 
 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 #define MAX_NUM_MCACHE 8
@@ -764,7 +765,9 @@ void hwss_build_fast_sequence(struct dc *dc,
        if (dc->hwss.dmub_hw_control_lock_fast) {
                block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
                block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;
-               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required =
+                       dc_state_is_fams2_in_use(dc, context) ||
+                       dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link);
                block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
                (*num_steps)++;
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index 39f5fa73c43e67c37774da5506f618979007e761..5bfa2b0d2afdc6df55e9c97fb5650f82f2b45e70 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -61,31 +61,49 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
        dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);
 }
 
-bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link)
+bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link)
 {
-       /* ASIC doesn't support DMUB */
-       if (!dc->ctx->dmub_srv)
+       if (!link)
                return false;
 
-       if (link) {
+       if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+               return true;
 
-               if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
-                       return true;
+       if (link->replay_settings.replay_feature_enabled)
+               return true;
 
-               if (link->replay_settings.replay_feature_enabled)
-                       return true;
+       if (link->psr_settings.psr_version == DC_PSR_VERSION_1) {
+               struct dc_link *edp_links[MAX_NUM_EDP];
+               int edp_num;
 
-                       /* only use HW lock for PSR1 on single eDP */
-               if (link->psr_settings.psr_version == DC_PSR_VERSION_1) {
-                       struct dc_link *edp_links[MAX_NUM_EDP];
-                       int edp_num;
+               dc_get_edp_links(dc, edp_links, &edp_num);
+               if (edp_num == 1)
+                       return true;
+       }
+       return false;
+}
 
-                       dc_get_edp_links(dc, edp_links, &edp_num);
+bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context)
+{
+       if (!context)
+               return false;
+       for (int i = 0; i < context->stream_count; i++) {
+               const struct dc_link *link = context->streams[i]->link;
 
-                       if (edp_num == 1)
-                               return true;
-               }
+               if (dmub_hw_lock_mgr_does_link_require_lock(dc, link))
+                       return true;
        }
-
        return false;
 }
+
+bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link)
+{
+       /* ASIC doesn't support DMUB */
+       if (!dc->ctx->dmub_srv)
+               return false;
+
+       if (dc->ctx->dce_version >= DCN_VERSION_4_01)
+               return false;
+
+       return dmub_hw_lock_mgr_does_link_require_lock(dc, link);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
index 9f53d2ea5fa59a6da82a855691cd5b416408986c..4c80ca8484ad3b2e118779f749af09150ce03902 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
@@ -46,5 +46,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
  * Return: true if the inbox1 lock should be used, false otherwise
  */
 bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link);
+bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link);
+bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context);
 
 #endif /*_DMUB_HW_LOCK_MGR_H_ */