drm/i915: do cck get/put inside vlv_get_cck_clock()

Move towards VLV/CHV clock interfaces that handle sideband get/put
inside them instead of at the caller.

With this, we can switch to the simpler vlv_punit_get()/vlv_punit_put()
in vlv_get_cdclk().

We'll need to move vlv_init_gpll_ref_freq() outside of the existing
get/put in vlv_rps_init() and chv_rps_init().

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/480b654b6c736a03343dfd17eb130c39fd82c637.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c54c7fd93f970ef02a8f7379747325cba05a1636..bf4e975ac41c4459bf9cf2f2f2bf141a3479f4b7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -609,17 +609,13 @@ static void vlv_get_cdclk(struct intel_display *display,
        u32 val;
 
        cdclk_config->vco = vlv_get_hpll_vco(display->drm);
-
-       vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
-
        cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",
                                                CCK_DISPLAY_CLOCK_CONTROL,
                                                cdclk_config->vco);
 
+       vlv_punit_get(display->drm);
        val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
-
-       vlv_iosf_sb_put(display->drm,
-                       BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
+       vlv_punit_put(display->drm);
 
        if (display->platform.valleyview)
                cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f5208583235ddc61730d22117defd2de81b42e3b..aef136a1be2582e112f92e40ba1bc008722e0c00 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -163,7 +163,10 @@ int vlv_get_cck_clock(struct drm_device *drm,
        u32 val;
        int divider;
 
+       vlv_cck_get(drm);
        val = vlv_cck_read(drm, reg);
+       vlv_cck_put(drm);
+
        divider = val & CCK_FREQUENCY_VALUES;
 
        drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
@@ -182,12 +185,8 @@ int vlv_get_cck_clock_hpll(struct drm_device *drm,
        if (dev_priv->hpll_freq == 0)
                dev_priv->hpll_freq = vlv_get_hpll_vco(drm);
 
-       vlv_cck_get(drm);
-
        hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq);
 
-       vlv_cck_put(drm);
-
        return hpll;
 }
 

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 4da94098bd3e5cb1d9fb562202050a5d74c670d4..afc934b7f5bcb6f2cf0b435796cdd89add9bc52b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1703,13 +1703,13 @@ static void vlv_rps_init(struct intel_rps *rps)
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
 
+       vlv_init_gpll_ref_freq(rps);
+
        vlv_iosf_sb_get(&i915->drm,
                        BIT(VLV_IOSF_SB_PUNIT) |
                        BIT(VLV_IOSF_SB_NC) |
                        BIT(VLV_IOSF_SB_CCK));
 
-       vlv_init_gpll_ref_freq(rps);
-
        rps->max_freq = vlv_rps_max_freq(rps);
        rps->rp0_freq = rps->max_freq;
        drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
@@ -1737,13 +1737,13 @@ static void chv_rps_init(struct intel_rps *rps)
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
 
+       vlv_init_gpll_ref_freq(rps);
+
        vlv_iosf_sb_get(&i915->drm,
                        BIT(VLV_IOSF_SB_PUNIT) |
                        BIT(VLV_IOSF_SB_NC) |
                        BIT(VLV_IOSF_SB_CCK));
 
-       vlv_init_gpll_ref_freq(rps);
-
        rps->max_freq = chv_rps_max_freq(rps);
        rps->rp0_freq = rps->max_freq;
        drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",