re PR target/59054 (Powerpc -O0 -mcpu=power7 generates sub-optimal code to load 0)

2013-11-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/59054
	* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
	specify an appropriate register class for VSX operations.
	(load_vsx): Use it.
	(load_gpr_to_vsx): Likewise.
	(load_vsx_to_gpr): Likewise.
	* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
	register class for VSX registers that the type can handle.  Remove
	checks for explicit number of instructions generated, just check
	if the instruction is generated.
	* gcc.target/powerpc/direct-move-vint2.c: Likewise.
	* gcc.target/powerpc/direct-move-float1.c: Likewise.
	* gcc.target/powerpc/direct-move-float2.c: Likewise.
	* gcc.target/powerpc/direct-move-double1.c: Likewise.
	* gcc.target/powerpc/direct-move-double2.c: Likewise.
	* gcc.target/powerpc/direct-move-long1.c: Likewise.
	* gcc.target/powerpc/direct-move-long2.c: Likewise.

	* gcc.target/powerpc/pr59054.c: Remove duplicate code.

	* gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
	* gcc.target/powerpc/bool3-p7.c: Likewise.
	* gcc.target/powerpc/bool3-p8.c: Likewise.

	* gcc.target/powerpc/p8vector-ldst.c: Just check that the
	appropriate instructions are generated, don't check the count.

From-SVN: r205278

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 38c359e1fe0379be6f9497573c5376a2c51584c0..a8b93310b88b6f64315e254c9f76ba66ac072d9c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,32 @@
+2013-11-22  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/59054
+       * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
+       specify an appropriate register class for VSX operations.
+       (load_vsx): Use it.
+       (load_gpr_to_vsx): Likewise.
+       (load_vsx_to_gpr): Likewise.
+       * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
+       register class for VSX registers that the type can handle.  Remove
+       checks for explicit number of instructions generated, just check
+       if the instruction is generated.
+       * gcc.target/powerpc/direct-move-vint2.c: Likewise.
+       * gcc.target/powerpc/direct-move-float1.c: Likewise.
+       * gcc.target/powerpc/direct-move-float2.c: Likewise.
+       * gcc.target/powerpc/direct-move-double1.c: Likewise.
+       * gcc.target/powerpc/direct-move-double2.c: Likewise.
+       * gcc.target/powerpc/direct-move-long1.c: Likewise.
+       * gcc.target/powerpc/direct-move-long2.c: Likewise.
+
+       * gcc.target/powerpc/pr59054.c: Remove duplicate code.
+
+       * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
+       * gcc.target/powerpc/bool3-p7.c: Likewise.
+       * gcc.target/powerpc/bool3-p8.c: Likewise.
+
+       * gcc.target/powerpc/p8vector-ldst.c: Just check that the
+       appropriate instructions are generated, don't check the count.
+
 2013-11-22  Richard Earnshaw  <rearnsha@arm.com>
 
        PR target/59216

diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-av.c b/gcc/testsuite/gcc.target/powerpc/bool3-av.c
index 4ef82c8cd970696f817ac6e229c062543905d884..d4aac786b2c796304ec1e1532b67e22b1582e4fb 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bool3-av.c
+++ b/gcc/testsuite/gcc.target/powerpc/bool3-av.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
 /* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */

diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-p7.c b/gcc/testsuite/gcc.target/powerpc/bool3-p7.c
index a077ba5aea7c839fadb187dbb17b88203056f69d..34e3c9e79dd356b586067729592aa01209911790 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bool3-p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/bool3-p7.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-options "-O2 -mcpu=power7" } */

diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c
index 361a0452d7da3bc9c223549a3276387e952803da..e1b2dfa7ee2b18e67b6632d6f3398b20b0eba7f4 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-O2 -mcpu=power8" } */

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
index 534a04a937b5b0c7eb710e7a58b88d2d76a3a9d1..2569ac84369cb5b2d8467eed516a95b61c7b7176 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
@@ -3,13 +3,14 @@
 /* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-mcpu=power8 -O2" } */
-/* { dg-final { scan-assembler-times "mtvsrd" 1 } } */
-/* { dg-final { scan-assembler-times "mfvsrd" 1 } } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
 
-/* Check code generation for direct move for long types.  */
+/* Check code generation for direct move for double types.  */
 
 #define TYPE double
 #define IS_FLOAT 1
 #define NO_ALTIVEC 1
+#define VSX_REG_ATTR "ws"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
index 750debfc0dfa72e6d6314158325bb93802ca7aac..c8702204b703f29c87542f269e49b3f68f3ccb04 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
@@ -10,5 +10,6 @@
 #define IS_FLOAT 1
 #define NO_ALTIVEC 1
 #define DO_MAIN
+#define VSX_REG_ATTR "ws"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
index ff1e97c0d43c5fea3ee4190cede27afca5332e36..524c0eead431eb8c52221e2d55d800499862a47f 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
@@ -3,15 +3,16 @@
 /* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-mcpu=power8 -O2" } */
-/* { dg-final { scan-assembler-times "mtvsrd" 2 } } */
-/* { dg-final { scan-assembler-times "mfvsrd" 2 } } */
-/* { dg-final { scan-assembler-times "xscvdpspn" 2 } } */
-/* { dg-final { scan-assembler-times "xscvspdpn" 2 } } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler "xscvdpspn" } } */
+/* { dg-final { scan-assembler "xscvspdpn" } } */
 
-/* Check code generation for direct move for long types.  */
+/* Check code generation for direct move for float types.  */
 
 #define TYPE float
 #define IS_FLOAT 1
 #define NO_ALTIVEC 1
+#define VSX_REG_ATTR "ww"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
index ace728ff6d4428e5f764c3869a688f3adbdd6f7e..352e76166d087e410f065c71593f4ad3f904d1e7 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
@@ -10,5 +10,6 @@
 #define IS_FLOAT 1
 #define NO_ALTIVEC 1
 #define DO_MAIN
+#define VSX_REG_ATTR "ww"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
index 907e802c72b216a75fccd13921c59574f133641a..0a78f9cb2586cd9b59da99cd6245f0c9bd1d62ec 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
@@ -3,13 +3,14 @@
 /* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-mcpu=power8 -O2" } */
-/* { dg-final { scan-assembler-times "mtvsrd" 1 } } */
-/* { dg-final { scan-assembler-times "mfvsrd" 2 } } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
 
 /* Check code generation for direct move for long types.  */
 
 #define TYPE long
 #define IS_INT 1
 #define NO_ALTIVEC 1
+#define VSX_REG_ATTR "d"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
index fba613e454824687d3bffe0ee77c6bf80e9ba532..cee9e0e0f1d210fcc234feb695d2c998621265cf 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
@@ -10,5 +10,6 @@
 #define IS_INT 1
 #define NO_ALTIVEC 1
 #define DO_MAIN
+#define VSX_REG_ATTR "d"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
index cdfa18857f14730aacb13bcf3e56d5f8453d1018..3067b9a8e627e0a4d940d253eb78114ac5454c6a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
@@ -3,11 +3,12 @@
 /* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-mcpu=power8 -O2" } */
-/* { dg-final { scan-assembler-times "mtvsrd" 4 } } */
-/* { dg-final { scan-assembler-times "mfvsrd" 4 } } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
 
-/* Check code generation for direct move for long types.  */
+/* Check code generation for direct move for vector types.  */
 
 #define TYPE vector int
+#define VSX_REG_ATTR "wa"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
index 5c0c9abdac5581bcd29ff010555991b6dfbda97e..0d8264faf7186150e28878a39760ec65f8393f35 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
@@ -8,5 +8,6 @@
 
 #define TYPE vector int
 #define DO_MAIN
+#define VSX_REG_ATTR "wa"
 
 #include "direct-move.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move.h b/gcc/testsuite/gcc.target/powerpc/direct-move.h
index c1709e6c7efb099d81daa29d86377c90e51d0134..6a5b7ba18061a6d87fd163bba2a4368c9055ff61 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/direct-move.h
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move.h
@@ -3,6 +3,10 @@
 #include <math.h>
 extern void abort (void);
 
+#ifndef VSX_REG_ATTR
+#define VSX_REG_ATTR "wa"
+#endif
+
 void __attribute__((__noinline__))
 copy (TYPE *a, TYPE *b)
 {
@@ -44,7 +48,7 @@ void __attribute__((__noinline__))
 load_vsx (TYPE *a, TYPE *b)
 {
   TYPE c = *a;
-  __asm__ ("# vsx, reg = %x0" : "+wa" (c));
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
   *b = c;
 }
 #endif
@@ -57,7 +61,7 @@ load_gpr_to_vsx (TYPE *a, TYPE *b)
   TYPE d;
   __asm__ ("# gpr, reg = %0" : "+b" (c));
   d = c;
-  __asm__ ("# vsx, reg = %x0" : "+wa" (d));
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));
   *b = d;
 }
 #endif
@@ -68,7 +72,7 @@ load_vsx_to_gpr (TYPE *a, TYPE *b)
 {
   TYPE c = *a;
   TYPE d;
-  __asm__ ("# vsx, reg = %x0" : "+wa" (c));
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
   d = c;
   __asm__ ("# gpr, reg = %0" : "+b" (d));
   *b = d;

diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
index d0b3eb09ef7e0c64fbfc6cae220e82b0dfd52e6a..33f19991f7611288b57434372cacf0b5b6bcc60a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
@@ -36,7 +36,7 @@ void store_df (double *p, double d)
   *p = d;
 }
 
-/* { dg-final { scan-assembler-times "lxsspx"  2 } } */
-/* { dg-final { scan-assembler-times "lxsdx"   1 } } */
-/* { dg-final { scan-assembler-times "stxsspx" 1 } } */
-/* { dg-final { scan-assembler-times "stxsdx"  1 } } */
+/* { dg-final { scan-assembler "lxsspx"  } } */
+/* { dg-final { scan-assembler "lxsdx"   } } */
+/* { dg-final { scan-assembler "stxsspx" } } */
+/* { dg-final { scan-assembler "stxsdx"  } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/pr59054.c b/gcc/testsuite/gcc.target/powerpc/pr59054.c
index 0379aeee63539f9cf31c9de4511b7feec4994b49..052f238ba0e92350318c26ee57a8098bedade2da 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr59054.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr59054.c
@@ -4,15 +4,3 @@
 /* { dg-options "-mcpu=power7 -O0 -m64" } */
 
 long foo (void) { return 0; }
-
-/* { dg-final { scan-assembler-not "xxlor" } } */
-/* { dg-final { scan-assembler-not "stfd" } } */
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mcpu=power7 -O0 -m64" } */
-
-long foo (void) { return 0; }
-
-/* { dg-final { scan-assembler-not "xxlor" } } */
-/* { dg-final { scan-assembler-not "stfd" } } */