+2009-01-07 Nathan Froyd <froydnj@codesourcery.com>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * config/rs6000/rs6000.c (rs6000_legitimize_address): Check for
+ non-word-aligned REG+CONST addressing.
+
2009-01-07 Uros Bizjak <ubizjak@gmail.com>
PR target/38706
&& GET_CODE (XEXP (x, 0)) == REG
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
- && !(SPE_VECTOR_MODE (mode)
+ && !((TARGET_POWERPC64
+ && (mode == DImode || mode == TImode)
+ && (INTVAL (XEXP (x, 1)) & 3) != 0)
+ || SPE_VECTOR_MODE (mode)
|| ALTIVEC_VECTOR_MODE (mode)
|| (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
|| mode == DImode || mode == DDmode
+2009-01-07 Nathan Froyd <froydnj@codesourcery.com>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * gcc.c-torture/compile/20090107-1.c: New test.
+
2009-01-07 Uros Bizjak <ubizjak@gmail.com>
PR target/38706
--- /dev/null
+/* Verify that we don't ICE by forming invalid addresses for unaligned
+ doubleword loads (originally for PPC64). */
+
+struct a
+{
+ unsigned int x;
+ unsigned short y;
+} __attribute__((packed));
+
+struct b {
+ struct a rep;
+ unsigned long long seq;
+} __attribute__((packed));
+
+struct c {
+ int x;
+ struct a a[5460];
+ struct b b;
+};
+
+extern void use_ull(unsigned long long);
+extern void f(struct c *i) {
+ use_ull(i->b.seq);
+ return;
+}