drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D

All the places that use DSPCLK_GATE_D are specific to certain platforms,
and the parametrization of it to support VLV/CHV MMIO display base isn't
really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D
and use it.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/ac16d9d5192595944bf9bcf70aa721b504bc90c0.1754499175.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6efe5524cbbf9de79258c9fe9505342b6acc7bcf..31c2a07bb1883868e6a857e10e99e258cfc348f4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1209,7 +1209,7 @@ static void vlv_init_display_clock_gating(struct intel_display *display)
         * (and never recovering) in this case. intel_dsi_post_disable() will
         * clear it when we turn off the display.
         */
-       intel_de_rmw(display, DSPCLK_GATE_D(display),
+       intel_de_rmw(display, VLV_DSPCLK_GATE_D,
                     ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
 
        /*

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6a74805570e1cf3c7d7f34809e064db482f9e903..063335053d13487a9f7004615f76cac6c0434e6b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -219,7 +219,7 @@ static void pnv_gmbus_clock_gating(struct intel_display *display,
                                   bool enable)
 {
        /* When using bit bashing for I2C, this bit needs to be set to 1 */
-       intel_de_rmw(display, DSPCLK_GATE_D(display),
+       intel_de_rmw(display, DSPCLK_GATE_D,
                     PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
                     !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
 }

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 159a5f998ea06ac617e6d4ed2ae80648bf6fb6d4..272f9e7af4d4412920bf3407637ddb8b2583a9fa 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -217,10 +217,9 @@ static void i830_overlay_clock_gating(struct intel_display *display,
 
        /* WA_OVERLAY_CLKGATE:alm */
        if (enable)
-               intel_de_write(display, DSPCLK_GATE_D(display), 0);
+               intel_de_write(display, DSPCLK_GATE_D, 0);
        else
-               intel_de_write(display, DSPCLK_GATE_D(display),
-                              OVRUNIT_CLOCK_GATE_DISABLE);
+               intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 
        /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
        pci_bus_read_config_byte(pdev->bus,

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 6d9f3312de7e45164cb862e6af8b199f39129b18..c9a53fde79c46847ef1b7ed5920b71e387dc5bca 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -761,7 +761,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 
        if (display->platform.valleyview || display->platform.cherryview) {
                /* Disable DPOunit clock gating, can stall pipe */
-               intel_de_rmw(display, DSPCLK_GATE_D(display),
+               intel_de_rmw(display, VLV_DSPCLK_GATE_D,
                             0, DPOUNIT_CLOCK_GATE_DISABLE);
        }
 
@@ -918,7 +918,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
        } else {
                vlv_dsi_pll_disable(encoder);
 
-               intel_de_rmw(display, DSPCLK_GATE_D(display),
+               intel_de_rmw(display, VLV_DSPCLK_GATE_D,
                             DPOUNIT_CLOCK_GATE_DISABLE, 0);
        }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03b895897f60031c1e9efe16ab67531d2e565b4f..b283b25d83688fb0cb30360cfb4ec4e8f1a97464 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,7 +613,8 @@
 #define  DSTATE_GFX_CLOCK_GATING               (1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING               (1 << 0)
 
-#define DSPCLK_GATE_D(__i915)          _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
+#define DSPCLK_GATE_D                  _MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D              _MMIO(VLV_DISPLAY_BASE + 0x6200)
 # define DPUNIT_B_CLOCK_GATE_DISABLE           (1 << 30) /* 965 */
 # define VSUNIT_CLOCK_GATE_DISABLE             (1 << 29) /* 965 */
 # define VRHUNIT_CLOCK_GATE_DISABLE            (1 << 28) /* 965 */

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index e501f49375107058de828fe68d9dd2139738a231..467740969431848d1acbd68177ba8e7d834c3235 100644 (file)
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -620,7 +620,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *i915)
                OVCUNIT_CLOCK_GATE_DISABLE;
        if (IS_GM45(i915))
                dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-       intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
+       intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
 
        g4x_disable_trickle_feed(i915);
 }
@@ -631,7 +631,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
 
        intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
        intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
-       intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
+       intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
        intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
        intel_uncore_write16(uncore, DEUC, 0);
        intel_uncore_write(uncore,