--- /dev/null
+From 6590fe323ce2807f5d9454e7fccf3fab875d4352 Mon Sep 17 00:00:00 2001
+From: Leorize <leorize+oss@disroot.org>
+Date: Wed, 27 May 2026 23:58:54 -0700
+Subject: drm/amd/display: add missing CSC entries for BT.2020 for DCE IPs
+
+From: Leorize <leorize+oss@disroot.org>
+
+commit 6590fe323ce2807f5d9454e7fccf3fab875d4352 upstream.
+
+DCE-based hardware does not have the CSC matrices for BT.2020, which
+causes the driver to fallback to the GPU built-in matrices. This does
+not appear to cause any issues for RGB sinks, but causes major color
+artifacts for YCbCr ones (e.g. black becomes green).
+
+This commit adds the missing CSC matrices (taken from DC common) to DCE
+CSC tables, resolving the issue.
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/3358
+Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5333
+Assisted-by: oh-my-pi:GPT-5.5
+Signed-off-by: Leorize <leorize+oss@disroot.org>
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 51e6668ab4baf55b082c376318d51ef965757196)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 10 +++++++++-
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c | 10 +++++++++-
+ 2 files changed, 18 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+@@ -110,7 +110,15 @@ static const struct out_csc_color_matrix
+ { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+ 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
+ { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+- 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
++ 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
++{ COLOR_SPACE_2020_RGB_FULLRANGE,
++ { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
++{ COLOR_SPACE_2020_RGB_LIMITEDRANGE,
++ { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} },
++{ COLOR_SPACE_2020_YCBCR_LIMITED, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868,
++ 0x15B2, 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} },
++{ COLOR_SPACE_2020_YCBCR_FULL, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2,
++ 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} }
+ };
+
+ static bool setup_scaling_configuration(
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
+@@ -88,7 +88,15 @@ static const struct out_csc_color_matrix
+ { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+ 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
+ { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+- 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
++ 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
++{ COLOR_SPACE_2020_RGB_FULLRANGE,
++ { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
++{ COLOR_SPACE_2020_RGB_LIMITEDRANGE,
++ { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} },
++{ COLOR_SPACE_2020_YCBCR_LIMITED, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868,
++ 0x15B2, 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} },
++{ COLOR_SPACE_2020_YCBCR_FULL, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2,
++ 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} }
+ };
+
+ enum csc_color_mode {
--- /dev/null
+From ff287df16a1a58aca78b08d1f3ee09fc44da0351 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Tue, 12 May 2026 15:24:22 -0400
+Subject: drm/amd/display: Bound VBIOS record-chain walk loops
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit ff287df16a1a58aca78b08d1f3ee09fc44da0351 upstream.
+
+[Why & How]
+All record-chain walk loops in bios_parser.c and bios_parser2.c use
+for(;;) and only terminate on a 0xFF record_type sentinel or zero
+record_size. A malformed VBIOS image missing the terminator record
+causes unbounded iteration at probe time, potentially hundreds of
+thousands of iterations with record_size=1. In the final iterations
+near the BIOS image boundary, struct casts beyond the 2-byte header
+validated by GET_IMAGE can also read out of bounds.
+
+Cap all 14 record-chain walk loops to BIOS_MAX_NUM_RECORD (256)
+iterations. The atombios.h defines up to 22 distinct record types
+and atomfirmware.h has 13. Assuming an average of less than 10
+records per type (which is reasonable since most are connector-
+based) 256 is a generous upper bound.
+
+Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
+Assisted-by: Copilot:claude-opus-4.6 Mythos
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 95700a3d660287ed657d6892f7be9ffc0e294a93)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 15 +++++---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 27 ++++++++++-----
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h | 5 ++
+ 3 files changed, 33 insertions(+), 14 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -220,6 +220,7 @@ static enum bp_result bios_parser_get_i2
+ ATOM_COMMON_RECORD_HEADER *header;
+ ATOM_I2C_RECORD *record;
+ struct bios_parser *bp = BP_FROM_DCB(dcb);
++ int i;
+
+ if (!info)
+ return BP_RESULT_BADINPUT;
+@@ -232,7 +233,7 @@ static enum bp_result bios_parser_get_i2
+ offset = le16_to_cpu(object->usRecordOffset)
+ + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
+
+ if (!header)
+@@ -291,11 +292,12 @@ static enum bp_result bios_parser_get_de
+ {
+ ATOM_COMMON_RECORD_HEADER *header;
+ uint32_t offset;
++ int i;
+
+ offset = le16_to_cpu(object->usRecordOffset)
+ + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
+
+ if (!header)
+@@ -868,6 +870,7 @@ static ATOM_HPD_INT_RECORD *get_hpd_reco
+ {
+ ATOM_COMMON_RECORD_HEADER *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -877,7 +880,7 @@ static ATOM_HPD_INT_RECORD *get_hpd_reco
+ offset = le16_to_cpu(object->usRecordOffset)
+ + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
+
+ if (!header)
+@@ -1572,6 +1575,7 @@ static ATOM_ENCODER_CAP_RECORD_V2 *get_e
+ {
+ ATOM_COMMON_RECORD_HEADER *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -1581,7 +1585,7 @@ static ATOM_ENCODER_CAP_RECORD_V2 *get_e
+ offset = le16_to_cpu(object->usRecordOffset)
+ + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
+
+ if (!header)
+@@ -2671,6 +2675,7 @@ static enum bp_result update_slot_layout
+ unsigned int record_offset)
+ {
+ unsigned int j;
++ unsigned int n;
+ struct bios_parser *bp;
+ ATOM_BRACKET_LAYOUT_RECORD *record;
+ ATOM_COMMON_RECORD_HEADER *record_header;
+@@ -2680,7 +2685,7 @@ static enum bp_result update_slot_layout
+ record = NULL;
+ record_header = NULL;
+
+- for (;;) {
++ for (n = 0; n < BIOS_MAX_NUM_RECORD; n++) {
+
+ record_header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, record_offset);
+ if (record_header == NULL) {
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -395,6 +395,7 @@ static enum bp_result bios_parser_get_i2
+ struct atom_i2c_record *record;
+ struct atom_i2c_record dummy_record = {0};
+ struct bios_parser *bp = BP_FROM_DCB(dcb);
++ int i;
+
+ if (!info)
+ return BP_RESULT_BADINPUT;
+@@ -428,7 +429,7 @@ static enum bp_result bios_parser_get_i2
+ break;
+ }
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -533,6 +534,7 @@ static struct atom_hpd_int_record *get_h
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -541,7 +543,7 @@ static struct atom_hpd_int_record *get_h
+
+ offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -610,6 +612,7 @@ static struct atom_hpd_int_record *get_h
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -619,7 +622,7 @@ static struct atom_hpd_int_record *get_h
+ offset = le16_to_cpu(object->disp_recordoffset)
+ + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -2177,6 +2180,7 @@ static struct atom_encoder_caps_record *
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -2185,7 +2189,7 @@ static struct atom_encoder_caps_record *
+
+ offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -2214,6 +2218,7 @@ static struct atom_disp_connector_caps_r
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -2222,7 +2227,7 @@ static struct atom_disp_connector_caps_r
+
+ offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -2250,6 +2255,7 @@ static struct atom_connector_caps_record
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -2258,7 +2264,7 @@ static struct atom_connector_caps_record
+
+ offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -2336,6 +2342,7 @@ static struct atom_connector_speed_recor
+ {
+ struct atom_common_record_header *header;
+ uint32_t offset;
++ int i;
+
+ if (!object) {
+ BREAK_TO_DEBUGGER(); /* Invalid object */
+@@ -2344,7 +2351,7 @@ static struct atom_connector_speed_recor
+
+ offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+- for (;;) {
++ for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
+ header = GET_IMAGE(struct atom_common_record_header, offset);
+
+ if (!header)
+@@ -3228,6 +3235,7 @@ static enum bp_result update_slot_layout
+ {
+ unsigned int record_offset;
+ unsigned int j;
++ unsigned int n;
+ struct atom_display_object_path_v2 *object;
+ struct atom_bracket_layout_record *record;
+ struct atom_common_record_header *record_header;
+@@ -3249,7 +3257,7 @@ static enum bp_result update_slot_layout
+ (object->disp_recordoffset) +
+ (unsigned int)(bp->object_info_tbl_offset);
+
+- for (;;) {
++ for (n = 0; n < BIOS_MAX_NUM_RECORD; n++) {
+
+ record_header = (struct atom_common_record_header *)
+ GET_IMAGE(struct atom_common_record_header,
+@@ -3343,6 +3351,7 @@ static enum bp_result update_slot_layout
+ struct slot_layout_info *slot_layout_info)
+ {
+ unsigned int record_offset;
++ unsigned int n;
+ struct atom_display_object_path_v3 *object;
+ struct atom_bracket_layout_record_v2 *record;
+ struct atom_common_record_header *record_header;
+@@ -3365,7 +3374,7 @@ static enum bp_result update_slot_layout
+ (object->disp_recordoffset) +
+ (unsigned int)(bp->object_info_tbl_offset);
+
+- for (;;) {
++ for (n = 0; n < BIOS_MAX_NUM_RECORD; n++) {
+
+ record_header = (struct atom_common_record_header *)
+ GET_IMAGE(struct atom_common_record_header,
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
+@@ -38,4 +38,9 @@ uint32_t bios_get_vga_enabled_displays(s
+
+ #define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type)))
+
++/* Upper bound on the number of records in a VBIOS record chain. Prevents
++ * unbounded looping if the VBIOS image is malformed and lacks a terminator.
++ */
++#define BIOS_MAX_NUM_RECORD 256
++
+ #endif
--- /dev/null
+From f0f3981c43b32cadfe373d636d9e9ca522bb3702 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Thu, 7 May 2026 15:38:37 -0400
+Subject: drm/amd/display: Clamp HDMI HDCP2 rx_id_list read to buffer size
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit f0f3981c43b32cadfe373d636d9e9ca522bb3702 upstream.
+
+[Why & How]
+During HDCP 2.x repeater authentication over HDMI, the driver reads the
+sink's RxStatus register and extracts a 10-bit message size field (max
+value 1023). This value is used as the read length for the ReceiverID
+list without being clamped to the size of the destination buffer
+rx_id_list[177]. A malicious HDMI repeater could advertise a message
+size larger than the buffer, causing an out-of-bounds write during the
+I2C read.
+
+Clamp the read length in mod_hdcp_read_rx_id_list() to the size of the
+rx_id_list buffer, matching the approach already used in the DP branch.
+
+Fixes: eff682f83c9c ("drm/amd/display: Add DDC handles for HDCP2.2")
+Assisted-by: Copilot:claude-opus-4.6
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 229212219e4247d9486f8ba41ef087358490be09)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -529,7 +529,8 @@ enum mod_hdcp_status mod_hdcp_read_rx_id
+ } else {
+ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
+ hdcp->auth.msg.hdcp2.rx_id_list,
+- hdcp->auth.msg.hdcp2.rx_id_list_size);
++ MIN(hdcp->auth.msg.hdcp2.rx_id_list_size,
++ sizeof(hdcp->auth.msg.hdcp2.rx_id_list)));
+ }
+ return status;
+ }
--- /dev/null
+From fb0707ce00eef4e2d60c3020e1c0432739703e4a Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Mon, 4 May 2026 15:51:13 -0400
+Subject: drm/amd/display: Clamp VBIOS HDMI retimer register count to array size
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit fb0707ce00eef4e2d60c3020e1c0432739703e4a upstream.
+
+[Why & How]
+The VBIOS integrated info tables (v1_11 and v2_1) contain HdmiRegNum and
+Hdmi6GRegNum fields that are used as loop bounds when copying retimer I2C
+register settings into fixed-size arrays (dp*_ext_hdmi_reg_settings[9]
+and dp*_ext_hdmi_6g_reg_settings[3]). These u8 fields are not validated
+before use, so a malformed VBIOS can specify values up to 255, causing an
+out-of-bounds heap write during driver probe.
+
+Clamp each register count to the destination array size using min_t()
+before the copy loops, in both get_integrated_info_v11() and
+get_integrated_info_v2_1().
+
+Assisted-by: GitHub Copilot:claude-opus-4.6
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 5a7f0ef90195940c54b0f5bb85b87da55f038c69)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 48 ++++++++++++++-------
+ 1 file changed, 32 insertions(+), 16 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -2591,14 +2591,16 @@ static enum bp_result get_integrated_inf
+ info_v11->extdispconninfo.checksum;
+
+ info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
+- info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
++ info->dp0_ext_hdmi_reg_num = min_t(u8, info_v11->dp0_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
++ info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp0_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
+ info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2607,14 +2609,16 @@ static enum bp_result get_integrated_inf
+ }
+
+ info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
+- info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
++ info->dp1_ext_hdmi_reg_num = min_t(u8, info_v11->dp1_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
++ info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp1_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
+ info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2623,14 +2627,16 @@ static enum bp_result get_integrated_inf
+ }
+
+ info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
+- info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
++ info->dp2_ext_hdmi_reg_num = min_t(u8, info_v11->dp2_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
++ info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp2_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
+ info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2639,14 +2645,16 @@ static enum bp_result get_integrated_inf
+ }
+
+ info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
+- info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
++ info->dp3_ext_hdmi_reg_num = min_t(u8, info_v11->dp3_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
++ info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp3_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
+ info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2796,14 +2804,16 @@ static enum bp_result get_integrated_inf
+ info->ext_disp_conn_info.checksum =
+ info_v2_1->extdispconninfo.checksum;
+ info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
+- info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
++ info->dp0_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
++ info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
+ info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2811,14 +2821,16 @@ static enum bp_result get_integrated_inf
+ info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
+- info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
++ info->dp1_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
++ info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
+ info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2826,14 +2838,16 @@ static enum bp_result get_integrated_inf
+ info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
+- info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
++ info->dp2_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
++ info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
+ info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+@@ -2841,14 +2855,16 @@ static enum bp_result get_integrated_inf
+ info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+ }
+ info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
+- info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
++ info->dp3_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.HdmiRegNum,
++ ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings));
+ for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+ info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
+ info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+ }
+- info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
++ info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.Hdmi6GRegNum,
++ ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings));
+ for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
+ info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+ info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
--- /dev/null
+From adf67034b1f61f7119295208085bfd43f85f56af Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Mon, 11 May 2026 16:46:25 -0400
+Subject: drm/amd/display: Fix NULL deref and buffer over-read in SDP debugfs
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit adf67034b1f61f7119295208085bfd43f85f56af upstream.
+
+[Why & How]
+dp_sdp_message_debugfs_write() dereferences connector->base.state->crtc
+without checking for NULL. A connector can be connected but not bound to
+any CRTC (e.g. after hot-plug before the next atomic commit), causing a
+kernel crash when writing to the sdp_message debugfs node.
+
+The function also ignores the user-provided size argument and always
+passes 36 bytes to copy_from_user(), reading past the user buffer when
+size < 36.
+
+Fix both issues by:
+- Returning -ENODEV when connector->base.state or state->crtc is NULL
+- Clamping write_size to min(size, sizeof(data))
+
+Fixes: c7ba3653e977 ("drm/amd/display: Generic SDP message access in amdgpu")
+Assisted-by: Copilot:claude-opus-4.6
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 6ab4c36a522842ff70474a1c0af2e40e50fc8300)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -1314,8 +1314,13 @@ static ssize_t dp_sdp_message_debugfs_wr
+ if (size == 0)
+ return 0;
+
++ if (!connector->base.state || !connector->base.state->crtc)
++ return -ENODEV;
++
+ acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
+
++ write_size = min_t(size_t, size, sizeof(data));
++
+ r = copy_from_user(data, buf, write_size);
+
+ write_size -= r;
--- /dev/null
+From da48bc4461b8a5ebfb9264c9b191a701d8e99009 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Tue, 5 May 2026 11:52:15 -0400
+Subject: drm/amd/display: Use krealloc_array() in dal_vector_reserve()
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit da48bc4461b8a5ebfb9264c9b191a701d8e99009 upstream.
+
+[Why & How]
+dal_vector_reserve() computes the allocation size as
+"capacity * vector->struct_size" using uint32_t arithmetic, which can
+silently wrap to a small value on overflow. This would cause krealloc to
+return a smaller buffer than expected, leading to heap overflows on
+subsequent vector appends.
+
+Replace krealloc() with krealloc_array() which performs an internal
+overflow check and returns NULL on wrap, preventing the issue.
+
+Fixes: 2004f45ef83f ("drm/amd/display: Use kernel alloc/free")
+Assisted-by: Copilot:claude-opus-4.6
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ray Wu <ray.wu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 37668568641ccc4cc1dbca4923d0a16609dd5707)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/basics/vector.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/basics/vector.c
++++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c
+@@ -288,8 +288,8 @@ bool dal_vector_reserve(struct vector *v
+ if (capacity <= vector->capacity)
+ return true;
+
+- new_container = krealloc(vector->container,
+- capacity * vector->struct_size, GFP_KERNEL);
++ new_container = krealloc_array(vector->container,
++ capacity, vector->struct_size, GFP_KERNEL);
+
+ if (new_container) {
+ vector->container = new_container;
--- /dev/null
+From bb204f19e4a115f094a6a3c4d82fcf48862d0766 Mon Sep 17 00:00:00 2001
+From: Yang Wang <kevinyang.wang@amd.com>
+Date: Tue, 19 May 2026 11:18:12 +0800
+Subject: drm/amd/pm: fix smu13 power limit default/cap calculation
+
+From: Yang Wang <kevinyang.wang@amd.com>
+
+commit bb204f19e4a115f094a6a3c4d82fcf48862d0766 upstream.
+
+smu_v13_0_0_get_power_limit() and smu_v13_0_7_get_power_limit() mix
+runtime power_limit with PP table limits when reporting default/min/max.
+
+When current power limit query succeeds, default_power_limit was set to the
+runtime value instead of the PP table default, and min/max could be derived
+from inconsistent bases (MsgLimits/runtime), leading to incorrect cap info.
+
+Use SocketPowerLimitAc/Dc as the PP default base (pp_limit), keep
+current_power_limit as runtime value, and derive min/max from pp_limit with
+OD percentages.
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5227
+Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 1eaf26db95901ca70737503a89b831dd763c8453)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 32 ++++++++++---------
+ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 32 ++++++++++---------
+ 2 files changed, 35 insertions(+), 29 deletions(-)
+
+--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+@@ -2383,28 +2383,30 @@ static int smu_v13_0_0_enable_mgpu_fan_b
+ }
+
+ static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
+- uint32_t *current_power_limit,
+- uint32_t *default_power_limit,
+- uint32_t *max_power_limit,
+- uint32_t *min_power_limit)
++ uint32_t *current_power_limit,
++ uint32_t *default_power_limit,
++ uint32_t *max_power_limit,
++ uint32_t *min_power_limit)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_13_0_0_powerplay_table *powerplay_table =
+ (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+ SkuTable_t *skutable = &pptable->SkuTable;
+- uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
+- uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
+-
+- if (smu_v13_0_get_current_power_limit(smu, &power_limit))
+- power_limit = smu->adev->pm.ac_power ?
++ uint32_t pp_limit = smu->adev->pm.ac_power ?
+ skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
+ skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
++ uint32_t power_limit = 0, od_percent_upper = 0, od_percent_lower = 0;
++ int ret;
++
++ if (current_power_limit) {
++ ret = smu_v13_0_get_current_power_limit(smu, &power_limit);
++ if (ret)
++ *current_power_limit = pp_limit;
++ }
+
+- if (current_power_limit)
+- *current_power_limit = power_limit;
+ if (default_power_limit)
+- *default_power_limit = power_limit;
++ *default_power_limit = pp_limit;
+
+ if (powerplay_table) {
+ if (smu->od_enabled &&
+@@ -2418,15 +2420,15 @@ static int smu_v13_0_0_get_power_limit(s
+ }
+
+ dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
+- od_percent_upper, od_percent_lower, power_limit);
++ od_percent_upper, od_percent_lower, pp_limit);
+
+ if (max_power_limit) {
+- *max_power_limit = msg_limit * (100 + od_percent_upper);
++ *max_power_limit = pp_limit * (100 + od_percent_upper);
+ *max_power_limit /= 100;
+ }
+
+ if (min_power_limit) {
+- *min_power_limit = power_limit * (100 - od_percent_lower);
++ *min_power_limit = pp_limit * (100 - od_percent_lower);
+ *min_power_limit /= 100;
+ }
+
+--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+@@ -2344,28 +2344,32 @@ static int smu_v13_0_7_enable_mgpu_fan_b
+ }
+
+ static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
+- uint32_t *current_power_limit,
+- uint32_t *default_power_limit,
+- uint32_t *max_power_limit,
+- uint32_t *min_power_limit)
++ uint32_t *current_power_limit,
++ uint32_t *default_power_limit,
++ uint32_t *max_power_limit,
++ uint32_t *min_power_limit)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_13_0_7_powerplay_table *powerplay_table =
+ (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+ SkuTable_t *skutable = &pptable->SkuTable;
+- uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
+- uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
+-
+- if (smu_v13_0_get_current_power_limit(smu, &power_limit))
+- power_limit = smu->adev->pm.ac_power ?
++ uint32_t pp_limit = smu->adev->pm.ac_power ?
+ skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
+ skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
++ uint32_t power_limit = 0, od_percent_upper = 0, od_percent_lower = 0;
++ int ret;
++
++ if (current_power_limit) {
++ ret = smu_v13_0_get_current_power_limit(smu, &power_limit);
++ if (ret)
++ power_limit = pp_limit;
+
+- if (current_power_limit)
+ *current_power_limit = power_limit;
++ }
++
+ if (default_power_limit)
+- *default_power_limit = power_limit;
++ *default_power_limit = pp_limit;
+
+ if (powerplay_table) {
+ if (smu->od_enabled &&
+@@ -2379,15 +2383,15 @@ static int smu_v13_0_7_get_power_limit(s
+ }
+
+ dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
+- od_percent_upper, od_percent_lower, power_limit);
++ od_percent_upper, od_percent_lower, pp_limit);
+
+ if (max_power_limit) {
+- *max_power_limit = msg_limit * (100 + od_percent_upper);
++ *max_power_limit = pp_limit * (100 + od_percent_upper);
+ *max_power_limit /= 100;
+ }
+
+ if (min_power_limit) {
+- *min_power_limit = power_limit * (100 - od_percent_lower);
++ *min_power_limit = pp_limit * (100 - od_percent_lower);
+ *min_power_limit /= 100;
+ }
+
--- /dev/null
+From ee193c5bbd5e2b56bbeb54ef554414b43a6fc896 Mon Sep 17 00:00:00 2001
+From: Yang Wang <kevinyang.wang@amd.com>
+Date: Fri, 29 May 2026 11:47:31 +0800
+Subject: drm/amd/pm: mark metrics.energy_accumulator is invalid for smu 14.0.2
+
+From: Yang Wang <kevinyang.wang@amd.com>
+
+commit ee193c5bbd5e2b56bbeb54ef554414b43a6fc896 upstream.
+
+EnergyAccumulator is unsupported on SMU 14.0.2, mark it invalid.
+
+Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
+Reviewed-by: Asad Kamal <asad.kamal@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 646b05043eeed04b51c14aad22a400a8250af4b7)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+@@ -2208,7 +2208,6 @@ static ssize_t smu_v14_0_2_get_gpu_metri
+ metrics->Vcn1ActivityPercentage);
+
+ gpu_metrics->average_socket_power = metrics->AverageSocketPower;
+- gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
+
+ if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
+ gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
--- /dev/null
+From 03b70e0d8aa26bab89a0f1394c1c80a871925e42 Mon Sep 17 00:00:00 2001
+From: Priya Hosur <Priya.Hosur@amd.com>
+Date: Thu, 7 May 2026 13:31:37 +0530
+Subject: drm/amd/pm: smu_v14_0_0: use SoftMin for gfxclk in set_soft_freq_limited_range
+
+From: Priya Hosur <Priya.Hosur@amd.com>
+
+commit 03b70e0d8aa26bab89a0f1394c1c80a871925e42 upstream.
+
+In smu_v14_0_0_set_soft_freq_limited_range(), the gfxclk floor is
+programmed via SetHardMinGfxClk together with SetSoftMaxGfxClk. Under
+power_dpm_force_performance_level=high this pins HardMin to peak gfxclk.
+
+In PMFW arbitration HardMin has higher priority than SoftMax, so the
+firmware thermal/PPT throttler cannot clamp gfxclk via SoftMax once
+HardMin is set to peak. Replace SetHardMinGfxClk with SetSoftMinGfxclk
+so the driver still requests peak performance but the firmware
+throttler retains the ability to clamp gfxclk under thermal/PPT
+pressure. SoftMax handling is unchanged and no other clock domains
+are affected.
+
+Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 3ea273267fd29cbf6d83ee72329f59eb5042605b)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+@@ -1219,7 +1219,8 @@ static int smu_v14_0_0_set_soft_freq_lim
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+- msg_set_min = SMU_MSG_SetHardMinGfxClk;
++ /* SoftMin lets PMFW throttle gfxclk; HardMin would override SoftMax. */
++ msg_set_min = SMU_MSG_SetSoftMinGfxclk;
+ msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
+ break;
+ case SMU_FCLK:
--- /dev/null
+From 40396ffdf6120e2380706c59e1a84d7e765a37b6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 25 Feb 2026 15:12:02 +0100
+Subject: drm/amdgpu: restart the CS if some parts of the VM are still invalidated
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Christian König <christian.koenig@amd.com>
+
+commit 40396ffdf6120e2380706c59e1a84d7e765a37b6 upstream.
+
+Make sure that we only submit work with full up to date VM page tables.
+
+Backport to 7.1 and older.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Tested-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 59720bfd8c6dbebeb8d5a7ab64241b007efd9213)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -1278,6 +1278,7 @@ static int amdgpu_cs_submit(struct amdgp
+ {
+ struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+ struct amdgpu_job *leader = p->gang_leader;
++ struct amdgpu_vm *vm = &fpriv->vm;
+ struct amdgpu_bo_list_entry *e;
+ struct drm_gem_object *gobj;
+ unsigned long index;
+@@ -1323,7 +1324,8 @@ static int amdgpu_cs_submit(struct amdgp
+ e->range);
+ e->range = NULL;
+ }
+- if (r) {
++
++ if (r || !list_empty(&vm->invalidated)) {
+ r = -EAGAIN;
+ mutex_unlock(&p->adev->notifier_lock);
+ return r;
--- /dev/null
+From 352ea59028ea48a6fff77f19ae28f98f71946a80 Mon Sep 17 00:00:00 2001
+From: Andrew Martin <andrew.martin@amd.com>
+Date: Thu, 28 May 2026 12:54:39 -0400
+Subject: drm/amdkfd: Fix buffer overflow in SDMA queue checkpoint/restore on GFX11
+
+From: Andrew Martin <andrew.martin@amd.com>
+
+commit 352ea59028ea48a6fff77f19ae28f98f71946a80 upstream.
+
+The v11 MQD manager incorrectly assigned the CP-compute variants of
+checkpoint_mqd/restore_mqd for KFD_MQD_TYPE_SDMA queues. These functions
+use sizeof(struct v11_compute_mqd) (2048 bytes) instead of sizeof(struct
+v11_sdma_mqd) (512 bytes), causing a 1536-byte overflow.
+
+During CRIU checkpoint of an SDMA queue on Navi3x:
+- checkpoint_mqd() reads 2048 bytes from a 512-byte SDMA MQD buffer,
+ leaking 1536 bytes of adjacent GTT memory to userspace
+
+During CRIU restore:
+- restore_mqd() writes 2048 bytes into a 512-byte SDMA MQD buffer,
+ corrupting 1536 bytes of adjacent GTT memory (often the ring buffer
+ or neighboring MQDs)
+
+This is a copy-paste regression unique to v11. All other ASIC backends
+(cik, vi, v9, v10, v12) correctly use the SDMA-specific variants.
+
+Add checkpoint_mqd_sdma() and restore_mqd_sdma() functions that properly
+handle the smaller v11_sdma_mqd structure, matching the pattern used in
+other MQD managers.
+
+Fixes: cc009e613de6 ("drm/amdkfd: Add KFD support for soc21 v3")
+Assisted-by: Claude:Sonnet 4-5
+Signed-off-by: Andrew Martin <andrew.martin@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 6fa41db7ffdec97d62433adf03b7b9b759af8c2c)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 49 +++++++++++++++++++----
+ 1 file changed, 41 insertions(+), 8 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+@@ -334,8 +334,7 @@ static void checkpoint_mqd(struct mqd_ma
+
+ static void restore_mqd(struct mqd_manager *mm, void **mqd,
+ struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+- struct queue_properties *qp,
+- const void *mqd_src,
++ struct queue_properties *qp, const void *mqd_src,
+ const void *ctl_stack_src, const u32 ctl_stack_size)
+ {
+ uint64_t addr;
+@@ -351,14 +350,48 @@ static void restore_mqd(struct mqd_manag
+ *gart_addr = addr;
+
+ m->cp_hqd_pq_doorbell_control =
+- qp->doorbell_off <<
+- CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
+- pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
+- m->cp_hqd_pq_doorbell_control);
++ qp->doorbell_off << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
++ pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", m->cp_hqd_pq_doorbell_control);
+
+ qp->is_active = 0;
+ }
+
++static void checkpoint_mqd_sdma(struct mqd_manager *mm,
++ void *mqd,
++ void *mqd_dst,
++ void *ctl_stack_dst)
++{
++ struct v11_sdma_mqd *m;
++
++ m = get_sdma_mqd(mqd);
++
++ memcpy(mqd_dst, m, sizeof(struct v11_sdma_mqd));
++}
++
++static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
++ struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
++ struct queue_properties *qp,
++ const void *mqd_src,
++ const void *ctl_stack_src,
++ const u32 ctl_stack_size)
++{
++ uint64_t addr;
++ struct v11_sdma_mqd *m;
++
++ m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr;
++ addr = mqd_mem_obj->gpu_addr;
++
++ memcpy(m, mqd_src, sizeof(*m));
++
++ m->sdmax_rlcx_doorbell_offset =
++ qp->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
++
++ *mqd = m;
++ if (gart_addr)
++ *gart_addr = addr;
++
++ qp->is_active = 0;
++}
+
+ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+@@ -543,8 +576,8 @@ struct mqd_manager *mqd_manager_init_v11
+ mqd->update_mqd = update_mqd_sdma;
+ mqd->destroy_mqd = kfd_destroy_mqd_sdma;
+ mqd->is_occupied = kfd_is_occupied_sdma;
+- mqd->checkpoint_mqd = checkpoint_mqd;
+- mqd->restore_mqd = restore_mqd;
++ mqd->checkpoint_mqd = checkpoint_mqd_sdma;
++ mqd->restore_mqd = restore_mqd_sdma;
+ mqd->mqd_size = sizeof(struct v11_sdma_mqd);
+ mqd->mqd_stride = kfd_mqd_stride;
+ #if defined(CONFIG_DEBUG_FS)
--- /dev/null
+From 2bd550b547deabef98bd3b017ff743b7c34d3a6d Mon Sep 17 00:00:00 2001
+From: Muhammad Bilal <meatuni001@gmail.com>
+Date: Sat, 23 May 2026 16:56:46 +0000
+Subject: drm/amdkfd: fix NULL dereference in get_queue_ids()
+
+From: Muhammad Bilal <meatuni001@gmail.com>
+
+commit 2bd550b547deabef98bd3b017ff743b7c34d3a6d upstream.
+
+When usr_queue_id_array is NULL and num_queues is non-zero,
+get_queue_ids() returns NULL. The callers check only IS_ERR() on the
+return value; since IS_ERR(NULL) == false the check passes, and
+suspend_queues() calls q_array_invalidate() which immediately
+dereferences NULL while iterating num_queues times.
+
+Userspace can trigger this via kfd_ioctl_set_debug_trap() by supplying
+num_queues > 0 with a zero queue_array_ptr, causing a kernel panic.
+
+A NULL usr_queue_id_array with num_queues == 0 is a legitimate no-op
+(q_array_invalidate never executes, and resume_queues already guards
+all queue_ids dereferences behind a NULL check). Return ERR_PTR(-EINVAL)
+only when num_queues is non-zero and the pointer is absent; both callers
+already propagate IS_ERR() returns correctly to userspace.
+
+Fixes: a70a93fa568b ("drm/amdkfd: add debug suspend and resume process queues operation")
+Signed-off-by: Muhammad Bilal <meatuni001@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit f165a82cdf503884bb1797771c61b2fcc72113d4)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -3195,7 +3195,7 @@ static void copy_context_work_handler (s
+ static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
+ {
+ if (!usr_queue_id_array)
+- return NULL;
++ return num_queues ? ERR_PTR(-EINVAL) : NULL;
+
+ if (num_queues > KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
+ return ERR_PTR(-EINVAL);
--- /dev/null
+From ae7676952790f421c40918e2586a2c9f12a682b6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
+Date: Tue, 2 Jun 2026 14:50:14 -0300
+Subject: drm/v3d: Fix vaddr leak when indirect CSD has zeroed workgroups
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Maíra Canal <mcanal@igalia.com>
+
+commit ae7676952790f421c40918e2586a2c9f12a682b6 upstream.
+
+v3d_rewrite_csd_job_wg_counts_from_indirect() maps both the indirect
+buffer and the workgroup buffer and is expected to release them before
+returning. When any of the workgroup counts read from the buffer is zero,
+the function bailed out early and skipped the cleanup, leaking the vaddr
+mappings of both BOs.
+
+Jump to the cleanup path instead of returning directly, so the mappings
+are always dropped.
+
+Cc: stable@vger.kernel.org
+Fixes: 18b8413b25b7 ("drm/v3d: Create a CPU job extension for a indirect CSD job")
+Suggested-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
+Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
+Link: https://patch.msgid.link/20260602-v3d-fix-indirect-csd-v4-1-654309e32bc0@igalia.com
+Signed-off-by: Maíra Canal <mcanal@igalia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/v3d/v3d_sched.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/v3d/v3d_sched.c
++++ b/drivers/gpu/drm/v3d/v3d_sched.c
+@@ -409,7 +409,7 @@ v3d_rewrite_csd_job_wg_counts_from_indir
+ wg_counts = (uint32_t *)(bo->vaddr + indirect_csd->offset);
+
+ if (wg_counts[0] == 0 || wg_counts[1] == 0 || wg_counts[2] == 0)
+- return;
++ goto unmap_bo;
+
+ args->cfg[0] = wg_counts[0] << V3D_CSD_CFG012_WG_COUNT_SHIFT;
+ args->cfg[1] = wg_counts[1] << V3D_CSD_CFG012_WG_COUNT_SHIFT;
+@@ -434,6 +434,7 @@ v3d_rewrite_csd_job_wg_counts_from_indir
+ }
+ }
+
++unmap_bo:
+ v3d_put_bo_vaddr(indirect);
+ v3d_put_bo_vaddr(bo);
+ }
--- /dev/null
+From 54f2a0442a30fe7a0f6bc8345e81f8b2db8effbd Mon Sep 17 00:00:00 2001
+From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
+Date: Wed, 3 Jun 2026 12:22:16 +0530
+Subject: drm/xe: Clear pending_disable before signaling suspend fence
+
+From: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
+
+commit 54f2a0442a30fe7a0f6bc8345e81f8b2db8effbd upstream.
+
+In the schedule-disable done path for suspend, we
+signal the suspend fence before clearing pending_disable.
+
+That wakeup can let suspend_wait complete and resume be queued
+immediately. The resume path may then reach enable_scheduling()
+while pending_disable is still set and hit the
+!exec_queue_pending_disable(q) assertion.
+
+Fix this by clearing pending_disable before signaling
+the suspend fence, so any resumed transition observes a
+consistent state.
+
+Fixes: 87651f31ae4e ("drm/xe/guc_submit: fix race around suspend_pending")
+Cc: stable@vger.kernel.org # v7.0+
+Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
+Reviewed-by: Thomas Hellstrom <thomas.hellstrom@linux.intel.com>
+Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
+Link: https://patch.msgid.link/20260603065217.3131066-3-tilak.tirumalesh.tangudu@intel.com
+(cherry picked from commit 4b1ae138b0e103d753773956a84eebc2edbf62c4)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/xe_guc_submit.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/xe/xe_guc_submit.c
++++ b/drivers/gpu/drm/xe/xe_guc_submit.c
+@@ -1907,8 +1907,8 @@ static void handle_sched_done(struct xe_
+ xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q));
+
+ if (q->guc->suspend_pending) {
+- suspend_fence_signal(q);
+ clear_exec_queue_pending_disable(q);
++ suspend_fence_signal(q);
+ } else {
+ if (exec_queue_banned(q) || check_timeout) {
+ smp_wmb();
slimbus-qcom-ngd-ctrl-correct-pdr-and-ssr-cleanup-ownership.patch
slimbus-qcom-ngd-ctrl-balance-pm_runtime-enablement-for-ngd.patch
slimbus-qcom-ngd-ctrl-avoid-abba-on-tx_lock-ctrl-lock.patch
+drm-amdkfd-fix-null-dereference-in-get_queue_ids.patch
+drm-amdkfd-fix-buffer-overflow-in-sdma-queue-checkpoint-restore-on-gfx11.patch
+drm-xe-clear-pending_disable-before-signaling-suspend-fence.patch
+drm-v3d-fix-vaddr-leak-when-indirect-csd-has-zeroed-workgroups.patch
+drm-amdgpu-restart-the-cs-if-some-parts-of-the-vm-are-still-invalidated.patch
+drm-amd-pm-fix-smu13-power-limit-default-cap-calculation.patch
+drm-amd-pm-mark-metrics.energy_accumulator-is-invalid-for-smu-14.0.2.patch
+drm-amd-pm-smu_v14_0_0-use-softmin-for-gfxclk-in-set_soft_freq_limited_range.patch
+drm-amd-display-bound-vbios-record-chain-walk-loops.patch
+drm-amd-display-clamp-hdmi-hdcp2-rx_id_list-read-to-buffer-size.patch
+drm-amd-display-clamp-vbios-hdmi-retimer-register-count-to-array-size.patch
+drm-amd-display-add-missing-csc-entries-for-bt.2020-for-dce-ips.patch
+drm-amd-display-fix-null-deref-and-buffer-over-read-in-sdp-debugfs.patch
+drm-amd-display-use-krealloc_array-in-dal_vector_reserve.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
