+++ /dev/null
-From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Date: Wed, 31 Jul 2024 11:59:12 +0530
-Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
-
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-
-commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream.
-
-The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
-value is greater than 0.5, the L value needs to be adjusted accordingly.
-Thus update the logic to handle the signed alpha val.
-
-Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
-Cc: stable@vger.kernel.org
-Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/clk/qcom/clk-alpha-pll.c
-+++ b/drivers/clk/qcom/clk-alpha-pll.c
-@@ -39,6 +39,7 @@
- #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
- # define PLL_POST_DIV_SHIFT 8
- # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
-+# define PLL_ALPHA_MSB BIT(15)
- # define PLL_ALPHA_EN BIT(24)
- # define PLL_ALPHA_MODE BIT(25)
- # define PLL_VCO_SHIFT 20
-@@ -1913,6 +1914,18 @@ static void clk_zonda_pll_disable(struct
- regmap_write(regmap, PLL_OPMODE(pll), 0x0);
- }
-
-+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
-+{
-+ u64 remainder, quotient;
-+
-+ quotient = rate;
-+ remainder = do_div(quotient, prate);
-+ *l = quotient;
-+
-+ if ((remainder * 2) / prate)
-+ *l = *l + 1;
-+}
-+
- static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
- {
-@@ -1929,6 +1942,9 @@ static int clk_zonda_pll_set_rate(struct
- if (ret < 0)
- return ret;
-
-+ if (a & PLL_ALPHA_MSB)
-+ zonda_pll_adjust_l_val(rate, prate, &l);
-+
- regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
- regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
-
clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch
-clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch
can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
tracing-avoid-possible-softlockup-in-tracing_iter_reset.patch
ila-call-nf_unregister_net_hooks-sooner.patch
+++ /dev/null
-From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Date: Wed, 31 Jul 2024 11:59:12 +0530
-Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
-
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-
-commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream.
-
-The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
-value is greater than 0.5, the L value needs to be adjusted accordingly.
-Thus update the logic to handle the signed alpha val.
-
-Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
-Cc: stable@vger.kernel.org
-Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/clk/qcom/clk-alpha-pll.c
-+++ b/drivers/clk/qcom/clk-alpha-pll.c
-@@ -41,6 +41,7 @@
- #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
- # define PLL_POST_DIV_SHIFT 8
- # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
-+# define PLL_ALPHA_MSB BIT(15)
- # define PLL_ALPHA_EN BIT(24)
- # define PLL_ALPHA_MODE BIT(25)
- # define PLL_VCO_SHIFT 20
-@@ -1986,6 +1987,18 @@ static void clk_zonda_pll_disable(struct
- regmap_write(regmap, PLL_OPMODE(pll), 0x0);
- }
-
-+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
-+{
-+ u64 remainder, quotient;
-+
-+ quotient = rate;
-+ remainder = do_div(quotient, prate);
-+ *l = quotient;
-+
-+ if ((remainder * 2) / prate)
-+ *l = *l + 1;
-+}
-+
- static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
- {
-@@ -2002,6 +2015,9 @@ static int clk_zonda_pll_set_rate(struct
- if (ret < 0)
- return ret;
-
-+ if (a & PLL_ALPHA_MSB)
-+ zonda_pll_adjust_l_val(rate, prate, &l);
-+
- regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
- regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
-
clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch
-clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch
can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
spi-rockchip-resolve-unbalanced-runtime-pm-system-pm-handling.patch
tracing-avoid-possible-softlockup-in-tracing_iter_reset.patch
+++ /dev/null
-From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Date: Wed, 31 Jul 2024 11:59:12 +0530
-Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
-
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-
-commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream.
-
-The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
-value is greater than 0.5, the L value needs to be adjusted accordingly.
-Thus update the logic to handle the signed alpha val.
-
-Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
-Cc: stable@vger.kernel.org
-Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/clk/qcom/clk-alpha-pll.c
-+++ b/drivers/clk/qcom/clk-alpha-pll.c
-@@ -41,6 +41,7 @@
- #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
- # define PLL_POST_DIV_SHIFT 8
- # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
-+# define PLL_ALPHA_MSB BIT(15)
- # define PLL_ALPHA_EN BIT(24)
- # define PLL_ALPHA_MODE BIT(25)
- # define PLL_VCO_SHIFT 20
-@@ -2070,6 +2071,18 @@ static void clk_zonda_pll_disable(struct
- regmap_write(regmap, PLL_OPMODE(pll), 0x0);
- }
-
-+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
-+{
-+ u64 remainder, quotient;
-+
-+ quotient = rate;
-+ remainder = do_div(quotient, prate);
-+ *l = quotient;
-+
-+ if ((remainder * 2) / prate)
-+ *l = *l + 1;
-+}
-+
- static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
- {
-@@ -2086,6 +2099,9 @@ static int clk_zonda_pll_set_rate(struct
- if (ret < 0)
- return ret;
-
-+ if (a & PLL_ALPHA_MSB)
-+ zonda_pll_adjust_l_val(rate, prate, &l);
-+
- regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
- regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
-
clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch
-clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch
pinctrl-qcom-x1e80100-bypass-pdc-wakeup-parent-for-now.patch
can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
mm-vmalloc-optimize-vmap_lazy_nr-arithmetic-when-purging-each-vmap_area.patch
+++ /dev/null
-From f4973130d255dd4811006f5822d4fa4d0de9d712 Mon Sep 17 00:00:00 2001
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Date: Wed, 31 Jul 2024 11:59:12 +0530
-Subject: clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL
-
-From: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-
-commit f4973130d255dd4811006f5822d4fa4d0de9d712 upstream.
-
-The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha
-value is greater than 0.5, the L value needs to be adjusted accordingly.
-Thus update the logic to handle the signed alpha val.
-
-Fixes: f21b6bfecc27 ("clk: qcom: clk-alpha-pll: add support for zonda pll")
-Cc: stable@vger.kernel.org
-Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20240731062916.2680823-5-quic_skakitap@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/clk/qcom/clk-alpha-pll.c
-+++ b/drivers/clk/qcom/clk-alpha-pll.c
-@@ -41,6 +41,7 @@
- #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
- # define PLL_POST_DIV_SHIFT 8
- # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
-+# define PLL_ALPHA_MSB BIT(15)
- # define PLL_ALPHA_EN BIT(24)
- # define PLL_ALPHA_MODE BIT(25)
- # define PLL_VCO_SHIFT 20
-@@ -2043,6 +2044,18 @@ static void clk_zonda_pll_disable(struct
- regmap_write(regmap, PLL_OPMODE(pll), 0x0);
- }
-
-+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
-+{
-+ u64 remainder, quotient;
-+
-+ quotient = rate;
-+ remainder = do_div(quotient, prate);
-+ *l = quotient;
-+
-+ if ((remainder * 2) / prate)
-+ *l = *l + 1;
-+}
-+
- static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
- {
-@@ -2059,6 +2072,9 @@ static int clk_zonda_pll_set_rate(struct
- if (ret < 0)
- return ret;
-
-+ if (a & PLL_ALPHA_MSB)
-+ zonda_pll_adjust_l_val(rate, prate, &l);
-+
- regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
- regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
-
clk-qcom-clk-alpha-pll-fix-the-pll-post-div-mask.patch
clk-qcom-clk-alpha-pll-fix-the-trion-pll-postdiv-set-rate-api.patch
clk-qcom-clk-alpha-pll-fix-zonda-set_rate-failure-when-pll-is-disabled.patch
-clk-qcom-clk-alpha-pll-update-set_rate-for-zonda-pll.patch
can-mcp251x-fix-deadlock-if-an-interrupt-occurs-during-mcp251x_open.patch
kexec_file-fix-elfcorehdr-digest-exclusion-when-config_crash_hotplug-y.patch
mm-vmalloc-ensure-vmap_block-is-initialised-before-adding-to-queue.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
