]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
6.1-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 3 Jul 2024 13:57:11 +0000 (15:57 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 3 Jul 2024 13:57:11 +0000 (15:57 +0200)
added patches:
serial-imx-only-set-receiver-level-if-it-is-zero.patch

queue-6.1/serial-imx-only-set-receiver-level-if-it-is-zero.patch [new file with mode: 0644]
queue-6.1/series

diff --git a/queue-6.1/serial-imx-only-set-receiver-level-if-it-is-zero.patch b/queue-6.1/serial-imx-only-set-receiver-level-if-it-is-zero.patch
new file mode 100644 (file)
index 0000000..9e5c261
--- /dev/null
@@ -0,0 +1,56 @@
+From 9706fc87b4cff0ac4f5d5d62327be83fe72e3108 Mon Sep 17 00:00:00 2001
+From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
+Date: Wed, 3 Jul 2024 13:25:40 +0200
+Subject: serial: imx: only set receiver level if it is zero
+
+From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
+
+commit 9706fc87b4cff0ac4f5d5d62327be83fe72e3108 upstream.
+
+With commit a81dbd0463ec ("serial: imx: set receiver level before
+starting uart") we set the receiver level to its default value. This
+caused a regression when using SDMA, where the receiver level is 9
+instead of 8 (default). This change will first check if the receiver
+level is zero and only then set it to the default. This still avoids the
+interrupt storm when the receiver level is zero.
+
+Fixes: a81dbd0463ec ("serial: imx: set receiver level before starting uart")
+Cc: stable <stable@kernel.org>
+Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
+Link: https://lore.kernel.org/r/20240703112543.148304-1-eichest@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/imx.c |    8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/tty/serial/imx.c
++++ b/drivers/tty/serial/imx.c
+@@ -120,6 +120,7 @@
+ #define UCR4_OREN     (1<<1)  /* Receiver overrun interrupt enable */
+ #define UCR4_DREN     (1<<0)  /* Recv data ready interrupt enable */
+ #define UFCR_RXTL_SHF 0       /* Receiver trigger level shift */
++#define UFCR_RXTL_MASK        0x3F    /* Receiver trigger 6 bits wide */
+ #define UFCR_DCEDTE   (1<<6)  /* DCE/DTE mode select */
+ #define UFCR_RFDIV    (7<<7)  /* Reference freq divider mask */
+ #define UFCR_RFDIV_REG(x)     (((x) < 7 ? 6 - (x) : 6) << 7)
+@@ -1959,7 +1960,7 @@ static int imx_uart_rs485_config(struct
+                                struct serial_rs485 *rs485conf)
+ {
+       struct imx_port *sport = (struct imx_port *)port;
+-      u32 ucr2;
++      u32 ucr2, ufcr;
+       if (rs485conf->flags & SER_RS485_ENABLED) {
+               /* Enable receiver if low-active RTS signal is requested */
+@@ -1979,7 +1980,10 @@ static int imx_uart_rs485_config(struct
+       /* Make sure Rx is enabled in case Tx is active with Rx disabled */
+       if (!(rs485conf->flags & SER_RS485_ENABLED) ||
+           rs485conf->flags & SER_RS485_RX_DURING_TX) {
+-              imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
++              /* If the receiver trigger is 0, set it to a default value */
++              ufcr = imx_uart_readl(sport, UFCR);
++              if ((ufcr & UFCR_RXTL_MASK) == 0)
++                      imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
+               imx_uart_start_rx(port);
+       }
index 90de273a3b4a081037215abbb2f7261ed8ad4d71..59d02b8a7077645721b3f6fec5c779a901693594 100644 (file)
@@ -126,3 +126,4 @@ arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch
 arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch
 arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch
 arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch
+serial-imx-only-set-receiver-level-if-it-is-zero.patch