PCI: Xilinx NWL PCIe Bridge: Modifying device tree node

Modifying device tree node to support legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index d03d066e03527798d5b0e7f1b407cb6e08781408..1c88a90c6386e25a193704ea60dc3cbcadd8683f 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -629,6 +629,16 @@
                              <0x0 0xe0000000 0x0 0x1000000>;
                        reg-names = "breg", "pcireg", "cfg";
                        ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+                       pcie_intc: legacy-interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
                };
 
                qspi: spi@ff0f0000 {