arm64: dts: hi3798cv200: fix the size of GICR

commit 428a575dc9038846ad259466d5ba109858c0a023 upstream.

During boot, Linux kernel complains:

[    0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set

This SoC is using a regular GIC-400 and the GICR space size should be
8KB rather than 256B.

With this patch:

[    0.000000] GIC: Using split EOI/Deactivate mode

So this should be the correct fix.

Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board")
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240219-cache-v3-1-a33c57534ae9@outlook.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 12bc1d3ed4243f5b50e2c4bfedacbd9def07cd4f..adc0a096ab4c4fae9bb78d17ef8e4b37a3dd3166 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,7 @@
        gic: interrupt-controller@f1001000 {
                compatible = "arm,gic-400";
                reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
-                     <0x0 0xf1002000 0x0 0x100>;   /* GICC */
+                     <0x0 0xf1002000 0x0 0x2000>;  /* GICC */
                #address-cells = <0>;
                #interrupt-cells = <3>;
                interrupt-controller;