]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: rtw89: pci: abstract RPP parser
authorPing-Ke Shih <pkshih@realtek.com>
Tue, 26 Aug 2025 08:53:24 +0000 (16:53 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Mon, 1 Sep 2025 02:54:15 +0000 (10:54 +0800)
RPP is short for release report of payload, which carries information
assisting TX completion. Since coming chips change the format, abstract
the parser ahead.

Don't change logic at all.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250826085324.28414-1-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/pci.c
drivers/net/wireless/realtek/rtw89/pci.h
drivers/net/wireless/realtek/rtw89/rtw8851be.c
drivers/net/wireless/realtek/rtw89/rtw8852ae.c
drivers/net/wireless/realtek/rtw89/rtw8852be.c
drivers/net/wireless/realtek/rtw89/rtw8852bte.c
drivers/net/wireless/realtek/rtw89/rtw8852ce.c
drivers/net/wireless/realtek/rtw89/rtw8922ae.c

index 55d82af732c007596b518a4ae606428a454ff349..cc54694859a6bf46e225fdef60b5fcda88c92bd0 100644 (file)
@@ -568,31 +568,40 @@ static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev,
                rtw89_pci_enqueue_txwd(tx_ring, txwd);
 }
 
-static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev,
-                                 struct rtw89_pci_rpp_fmt *rpp)
+void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
+                        struct rtw89_pci_rpp_info *rpp_info)
+{
+       const struct rtw89_pci_rpp_fmt *rpp = _rpp;
+
+       rpp_info->seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
+       rpp_info->qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
+       rpp_info->tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
+       rpp_info->txch = rtw89_core_get_ch_dma(rtwdev, rpp_info->qsel);
+}
+EXPORT_SYMBOL(rtw89_pci_parse_rpp);
+
+static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp)
 {
        struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
-       struct rtw89_pci_tx_ring *tx_ring;
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
+       struct rtw89_pci_rpp_info rpp_info = {};
        struct rtw89_pci_tx_wd_ring *wd_ring;
+       struct rtw89_pci_tx_ring *tx_ring;
        struct rtw89_pci_tx_wd *txwd;
-       u16 seq;
-       u8 qsel, tx_status, txch;
 
-       seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
-       qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
-       tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
-       txch = rtw89_core_get_ch_dma(rtwdev, qsel);
+       info->parse_rpp(rtwdev, rpp, &rpp_info);
 
-       if (txch == RTW89_TXCH_CH12) {
+       if (rpp_info.txch == RTW89_TXCH_CH12) {
                rtw89_warn(rtwdev, "should no fwcmd release report\n");
                return;
        }
 
-       tx_ring = &rtwpci->tx.rings[txch];
+       tx_ring = &rtwpci->tx.rings[rpp_info.txch];
        wd_ring = &tx_ring->wd_ring;
-       txwd = &wd_ring->pages[seq];
+       txwd = &wd_ring->pages[rpp_info.seq];
 
-       rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status);
+       rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, rpp_info.seq,
+                                  rpp_info.tx_status);
 }
 
 static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev,
@@ -617,13 +626,14 @@ static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,
                                     u32 max_cnt)
 {
        struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
-       struct rtw89_pci_rx_info *rx_info;
-       struct rtw89_pci_rpp_fmt *rpp;
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
        struct rtw89_rx_desc_info desc_info = {};
+       struct rtw89_pci_rx_info *rx_info;
        struct sk_buff *skb;
-       u32 cnt = 0;
-       u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt);
+       void *rpp;
        u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info);
+       u32 rpp_size = info->rpp_fmt_size;
+       u32 cnt = 0;
        u32 skb_idx;
        u32 offset;
        int ret;
@@ -649,7 +659,7 @@ static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,
        /* first segment has RX desc */
        offset = desc_info.offset + desc_info.rxd_len;
        for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
-               rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
+               rpp = skb->data + offset;
                rtw89_pci_release_rpp(rtwdev, rpp);
        }
 
index e8a856537b7c51ffeceb4e8efcd1499784b1b4e9..b0c6f4d38bf58c78ccf210762c20c9e309424d8e 100644 (file)
@@ -1365,6 +1365,13 @@ struct rtw89_pci_ssid_quirk {
        unsigned long bitmap; /* bitmap of rtw89_quirks */
 };
 
+struct rtw89_pci_rpp_info {
+       u16 seq;
+       u8 qsel;
+       u8 tx_status;
+       u8 txch;
+};
+
 struct rtw89_pci_info {
        const struct rtw89_pci_gen_def *gen_def;
        const struct rtw89_pci_isr_def *isr_def;
@@ -1386,6 +1393,7 @@ struct rtw89_pci_info {
        bool check_rx_tag;
        bool no_rxbd_fs;
        bool group_bd_addr;
+       u32 rpp_fmt_size;
 
        u32 init_cfg_reg;
        u32 txhci_en_bit;
@@ -1415,6 +1423,8 @@ struct rtw89_pci_info {
        u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
                                void *txaddr_info_addr, u32 total_len,
                                dma_addr_t dma, u8 *add_info_nr);
+       void (*parse_rpp)(struct rtw89_dev *rtwdev, void *rpp,
+                         struct rtw89_pci_rpp_info *rpp_info);
        void (*config_intr_mask)(struct rtw89_dev *rtwdev);
        void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
        void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
@@ -1724,6 +1734,8 @@ u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
                                  void *txaddr_info_addr, u32 total_len,
                                  dma_addr_t dma, u8 *add_info_nr);
+void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
+                        struct rtw89_pci_rpp_info *rpp_info);
 void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
index d2ea1e237a1f3b23201e0ee514b9763eb6375e59..ce59ac9f56ba87a3cb747266643e5777e44dfc39 100644 (file)
@@ -30,6 +30,7 @@ static const struct rtw89_pci_info rtw8851b_pci_info = {
        .check_rx_tag           = false,
        .no_rxbd_fs             = false,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_AX_PCIE_INIT_CFG1,
        .txhci_en_bit           = B_AX_TXHCI_EN,
@@ -59,6 +60,7 @@ static const struct rtw89_pci_info rtw8851b_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask,
        .enable_intr            = rtw89_pci_enable_intr,
        .disable_intr           = rtw89_pci_disable_intr,
index d733264b5dd1834f6e7b34b1782bb67bc0203955..9e05e831569d232531e411c7d9d595fb2dc7b25e 100644 (file)
@@ -30,6 +30,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
        .check_rx_tag           = false,
        .no_rxbd_fs             = false,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_AX_PCIE_INIT_CFG1,
        .txhci_en_bit           = B_AX_TXHCI_EN,
@@ -57,6 +58,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask,
        .enable_intr            = rtw89_pci_enable_intr,
        .disable_intr           = rtw89_pci_disable_intr,
index 146a1f2292d7c3e09bb003f99d7473a4701132b9..12db0d0be5479b511421e4c2f5c550f4ca1be2ae 100644 (file)
@@ -30,6 +30,7 @@ static const struct rtw89_pci_info rtw8852b_pci_info = {
        .check_rx_tag           = false,
        .no_rxbd_fs             = false,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_AX_PCIE_INIT_CFG1,
        .txhci_en_bit           = B_AX_TXHCI_EN,
@@ -59,6 +60,7 @@ static const struct rtw89_pci_info rtw8852b_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask,
        .enable_intr            = rtw89_pci_enable_intr,
        .disable_intr           = rtw89_pci_disable_intr,
index 5373b13e34708f09a345e27819305f0d00970ce6..8c995aa953251fd12ae675826f7fe93e664a61c2 100644 (file)
@@ -36,6 +36,7 @@ static const struct rtw89_pci_info rtw8852bt_pci_info = {
        .check_rx_tag           = false,
        .no_rxbd_fs             = false,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_AX_PCIE_INIT_CFG1,
        .txhci_en_bit           = B_AX_TXHCI_EN,
@@ -65,6 +66,7 @@ static const struct rtw89_pci_info rtw8852bt_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask,
        .enable_intr            = rtw89_pci_enable_intr,
        .disable_intr           = rtw89_pci_disable_intr,
index b2bf4ba6ddd84bcf3c881740480f5f60171c3d2e..150fed189414d35889202b94a9267373e77543e4 100644 (file)
@@ -39,6 +39,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
        .check_rx_tag           = false,
        .no_rxbd_fs             = false,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_AX_HAXI_INIT_CFG1,
        .txhci_en_bit           = B_AX_TXHCI_EN_V1,
@@ -66,6 +67,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set_v1,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info_v1,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask_v1,
        .enable_intr            = rtw89_pci_enable_intr_v1,
        .disable_intr           = rtw89_pci_disable_intr_v1,
index 32144fc66e4ad83a76baa78ce8bd8403b84b61e5..90c62b757c57bd0157ab143c2ae05702a0eb3777 100644 (file)
@@ -36,6 +36,7 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
        .check_rx_tag           = true,
        .no_rxbd_fs             = true,
        .group_bd_addr          = false,
+       .rpp_fmt_size           = sizeof(struct rtw89_pci_rpp_fmt),
 
        .init_cfg_reg           = R_BE_HAXI_INIT_CFG1,
        .txhci_en_bit           = B_BE_TXDMA_EN,
@@ -63,6 +64,7 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
 
        .ltr_set                = rtw89_pci_ltr_set_v2,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info_v1,
+       .parse_rpp              = rtw89_pci_parse_rpp,
        .config_intr_mask       = rtw89_pci_config_intr_mask_v2,
        .enable_intr            = rtw89_pci_enable_intr_v2,
        .disable_intr           = rtw89_pci_disable_intr_v2,