media: qcom: camss: csid-340: Switch to generic CSID_CFG/CTRL registers

The former RDI-specific register definitions (CSID_RDI_CFG0/CTRL) are
renamed to unified CSID_CFG0/CSID_CTRL variants, as their layout is
interface agnostic. This refactoring provides the foundation for
extending csid-340 with missing PIX interface/path support.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>

diff --git a/drivers/media/platform/qcom/camss/camss-csid-340.c b/drivers/media/platform/qcom/camss/camss-csid-340.c
index 0231985746edff9c32c5627a5cb089898ff6a2a8..9eee23bd81c2a59e4e2300c0b0209f3b2306a922 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-csid-340.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-340.c
@@ -41,19 +41,20 @@
 #define                CSI2_RX_CFG1_MISR_EN                    BIT(6)
 #define                CSI2_RX_CFG1_CGC_MODE                   BIT(7)
 
-#define CSID_RDI_CFG0(rdi)                                     (0x300 + 0x100 * (rdi))
-#define                CSID_RDI_CFG0_BYTE_CNTR_EN              BIT(0)
-#define                CSID_RDI_CFG0_TIMESTAMP_EN              BIT(1)
-#define                CSID_RDI_CFG0_DECODE_FORMAT_MASK        GENMASK(15, 12)
-#define                CSID_RDI_CFG0_DECODE_FORMAT_NOP         CSID_RDI_CFG0_DECODE_FORMAT_MASK
-#define                CSID_RDI_CFG0_DT_MASK                   GENMASK(21, 16)
-#define                CSID_RDI_CFG0_VC_MASK                   GENMASK(23, 22)
-#define                CSID_RDI_CFG0_DTID_MASK                 GENMASK(28, 27)
-#define                CSID_RDI_CFG0_ENABLE                    BIT(31)
-
-#define CSID_RDI_CTRL(rdi)                                     (0x308 + 0x100 * (rdi))
-#define CSID_RDI_CTRL_HALT_AT_FRAME_BOUNDARY           0
-#define CSID_RDI_CTRL_RESUME_AT_FRAME_BOUNDARY         1
+#define CSID_CFG0(iface)                                       (0x300 + 0x100 * (iface))
+#define                CSID_CFG0_BYTE_CNTR_EN                  BIT(0)
+#define                CSID_CFG0_TIMESTAMP_EN                  BIT(1)
+#define                CSID_CFG0_DECODE_FORMAT_MASK            GENMASK(15, 12)
+#define                CSID_CFG0_DECODE_FORMAT_NOP             CSID_CFG0_DECODE_FORMAT_MASK
+#define                CSID_CFG0_DT_MASK                       GENMASK(21, 16)
+#define                CSID_CFG0_VC_MASK                       GENMASK(23, 22)
+#define                CSID_CFG0_DTID_MASK                     GENMASK(28, 27)
+#define                CSID_CFG0_ENABLE                        BIT(31)
+
+#define CSID_CTRL(iface)                                       (0x308 + 0x100 * (iface))
+#define CSID_CTRL_HALT_AT_FRAME_BOUNDARY               0
+#define CSID_CTRL_RESUME_AT_FRAME_BOUNDARY             1
+
 
 static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy)
 {
@@ -71,7 +72,7 @@ static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config
 
 static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
 {
-       writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
+       writel_relaxed(!!enable, csid->base + CSID_CTRL(rdi));
 }
 
 static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc)
@@ -88,7 +89,7 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
         * the four least significant bits of the five bit VC
         * bitfield to generate an internal CID value.
         *
-        * CSID_RDI_CFG0(port)
+        * CSID_CFG0(port)
         * DT_ID : 28:27
         * VC    : 26:22
         * DT    : 21:16
@@ -97,19 +98,19 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8
         */
        dt_id = port & 0x03;
 
-       val = CSID_RDI_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
-       val |= FIELD_PREP(CSID_RDI_CFG0_DT_MASK, format->data_type);
-       val |= FIELD_PREP(CSID_RDI_CFG0_VC_MASK, vc);
-       val |= FIELD_PREP(CSID_RDI_CFG0_DTID_MASK, dt_id);
+       val = CSID_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
+       val |= FIELD_PREP(CSID_CFG0_DT_MASK, format->data_type);
+       val |= FIELD_PREP(CSID_CFG0_VC_MASK, vc);
+       val |= FIELD_PREP(CSID_CFG0_DTID_MASK, dt_id);
 
        if (enable)
-               val |= CSID_RDI_CFG0_ENABLE;
+               val |= CSID_CFG0_ENABLE;
 
        dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x port=%u vc=%u)\n",
                csid->id, enable ? "enable" : "disable", format->data_type,
                port, vc);
 
-       writel_relaxed(val, csid->base + CSID_RDI_CFG0(port));
+       writel_relaxed(val, csid->base + CSID_CFG0(port));
 }
 
 static void csid_configure_stream(struct csid_device *csid, u8 enable)