--- /dev/null
+From 9cc205e3c17d5716da7ebb7fa0c985555e95d009 Mon Sep 17 00:00:00 2001
+From: "Maciej W. Rozycki" <macro@orcam.me.uk>
+Date: Thu, 22 Sep 2022 22:56:06 +0100
+Subject: RISC-V: Make port I/O string accessors actually work
+
+From: Maciej W. Rozycki <macro@orcam.me.uk>
+
+commit 9cc205e3c17d5716da7ebb7fa0c985555e95d009 upstream.
+
+Fix port I/O string accessors such as `insb', `outsb', etc. which use
+the physical PCI port I/O address rather than the corresponding memory
+mapping to get at the requested location, which in turn breaks at least
+accesses made by our parport driver to a PCIe parallel port such as:
+
+PCI parallel port detected: 1415:c118, I/O at 0x1000(0x1008), IRQ 20
+parport0: PC-style at 0x1000 (0x1008), irq 20, using FIFO [PCSPP,TRISTATE,COMPAT,EPP,ECP]
+
+causing a memory access fault:
+
+Unable to handle kernel access to user memory without uaccess routines at virtual address 0000000000001008
+Oops [#1]
+Modules linked in:
+CPU: 1 PID: 350 Comm: cat Not tainted 6.0.0-rc2-00283-g10d4879f9ef0-dirty #23
+Hardware name: SiFive HiFive Unmatched A00 (DT)
+epc : parport_pc_fifo_write_block_pio+0x266/0x416
+ ra : parport_pc_fifo_write_block_pio+0xb4/0x416
+epc : ffffffff80542c3e ra : ffffffff80542a8c sp : ffffffd88899fc60
+ gp : ffffffff80fa2700 tp : ffffffd882b1e900 t0 : ffffffd883d0b000
+ t1 : ffffffffff000002 t2 : 4646393043330a38 s0 : ffffffd88899fcf0
+ s1 : 0000000000001000 a0 : 0000000000000010 a1 : 0000000000000000
+ a2 : ffffffd883d0a010 a3 : 0000000000000023 a4 : 00000000ffff8fbb
+ a5 : ffffffd883d0a001 a6 : 0000000100000000 a7 : ffffffc800000000
+ s2 : ffffffffff000002 s3 : ffffffff80d28880 s4 : ffffffff80fa1f50
+ s5 : 0000000000001008 s6 : 0000000000000008 s7 : ffffffd883d0a000
+ s8 : 0004000000000000 s9 : ffffffff80dc1d80 s10: ffffffd8807e4000
+ s11: 0000000000000000 t3 : 00000000000000ff t4 : 393044410a303930
+ t5 : 0000000000001000 t6 : 0000000000040000
+status: 0000000200000120 badaddr: 0000000000001008 cause: 000000000000000f
+[<ffffffff80543212>] parport_pc_compat_write_block_pio+0xfe/0x200
+[<ffffffff8053bbc0>] parport_write+0x46/0xf8
+[<ffffffff8050530e>] lp_write+0x158/0x2d2
+[<ffffffff80185716>] vfs_write+0x8e/0x2c2
+[<ffffffff80185a74>] ksys_write+0x52/0xc2
+[<ffffffff80185af2>] sys_write+0xe/0x16
+[<ffffffff80003770>] ret_from_syscall+0x0/0x2
+---[ end trace 0000000000000000 ]---
+
+For simplicity address the problem by adding PCI_IOBASE to the physical
+address requested in the respective wrapper macros only, observing that
+the raw accessors such as `__insb', `__outsb', etc. are not supposed to
+be used other than by said macros. Remove the cast to `long' that is no
+longer needed on `addr' now that it is used as an offset from PCI_IOBASE
+and add parentheses around `addr' needed for predictable evaluation in
+macro expansion. No need to make said adjustments in separate changes
+given that current code is gravely broken and does not ever work.
+
+Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
+Fixes: fab957c11efe2 ("RISC-V: Atomic and Locking Code")
+Cc: stable@vger.kernel.org # v4.15+
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Link: https://lore.kernel.org/r/alpine.DEB.2.21.2209220223080.29493@angie.orcam.me.uk
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/io.h | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/riscv/include/asm/io.h
++++ b/arch/riscv/include/asm/io.h
+@@ -252,9 +252,9 @@ __io_reads_ins(reads, u32, l, __io_br(),
+ __io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
+ __io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
+ __io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
+-#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
+-#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
+-#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
++#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
++#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
++#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)
+
+ __io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
+ __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
+@@ -266,22 +266,22 @@ __io_writes_outs(writes, u32, l, __io_bw
+ __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
+ __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
+ __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
+-#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
+-#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
+-#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
++#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
++#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
++#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)
+
+ #ifdef CONFIG_64BIT
+ __io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
+ #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
+
+ __io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
+-#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
++#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)
+
+ __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
+ #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
+
+ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
+-#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
++#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
+ #endif
+
+ #include <asm-generic/io.h>
--- /dev/null
+From 9e2e6042a7ec6504fe8e366717afa2f40cf16488 Mon Sep 17 00:00:00 2001
+From: Andrew Bresticker <abrestic@rivosinc.com>
+Date: Thu, 15 Sep 2022 15:37:02 -0400
+Subject: riscv: Allow PROT_WRITE-only mmap()
+
+From: Andrew Bresticker <abrestic@rivosinc.com>
+
+commit 9e2e6042a7ec6504fe8e366717afa2f40cf16488 upstream.
+
+Commit 2139619bcad7 ("riscv: mmap with PROT_WRITE but no PROT_READ is
+invalid") made mmap() return EINVAL if PROT_WRITE was set wihtout
+PROT_READ with the justification that a write-only PTE is considered a
+reserved PTE permission bit pattern in the privileged spec. This check
+is unnecessary since we let VM_WRITE imply VM_READ on RISC-V, and it is
+inconsistent with other architectures that don't support write-only PTEs,
+creating a potential software portability issue. Just remove the check
+altogether and let PROT_WRITE imply PROT_READ as is the case on other
+architectures.
+
+Note that this also allows PROT_WRITE|PROT_EXEC mappings which were
+disallowed prior to the aforementioned commit; PROT_READ is implied in
+such mappings as well.
+
+Fixes: 2139619bcad7 ("riscv: mmap with PROT_WRITE but no PROT_READ is invalid")
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20220915193702.2201018-3-abrestic@rivosinc.com/
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/kernel/sys_riscv.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/arch/riscv/kernel/sys_riscv.c
++++ b/arch/riscv/kernel/sys_riscv.c
+@@ -18,9 +18,6 @@ static long riscv_sys_mmap(unsigned long
+ if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
+ return -EINVAL;
+
+- if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ)))
+- return -EINVAL;
+-
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - page_shift_offset));
+ }
--- /dev/null
+From 3cebf80e9a0d3adcb174053be32c88a640b3344b Mon Sep 17 00:00:00 2001
+From: Fangrui Song <maskray@google.com>
+Date: Sun, 18 Sep 2022 02:29:34 -0700
+Subject: riscv: Pass -mno-relax only on lld < 15.0.0
+
+From: Fangrui Song <maskray@google.com>
+
+commit 3cebf80e9a0d3adcb174053be32c88a640b3344b upstream.
+
+lld since llvm:6611d58f5bbc ("[ELF] Relax R_RISCV_ALIGN"), which will be
+included in the 15.0.0 release, has implemented some RISC-V linker
+relaxation. -mno-relax is no longer needed in
+KBUILD_CFLAGS/KBUILD_AFLAGS to suppress R_RISCV_ALIGN which older lld
+can not handle:
+
+ ld.lld: error: capability.c:(.fixup+0x0): relocation R_RISCV_ALIGN
+ requires unimplemented linker relaxation; recompile with -mno-relax
+ but the .o is already compiled with -mno-relax
+
+Signed-off-by: Fangrui Song <maskray@google.com>
+Link: https://lore.kernel.org/r/20220710071117.446112-1-maskray@google.com/
+Link: https://lore.kernel.org/r/20220918092933.19943-1-palmer@rivosinc.com
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nathan Chancellor <nathan@kernel.org>
+Tested-by: Conor Dooley <conor.dooley@microchip.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/Makefile | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -35,6 +35,7 @@ else
+ endif
+
+ ifeq ($(CONFIG_LD_IS_LLD),y)
++ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 150000; echo $$?),0)
+ KBUILD_CFLAGS += -mno-relax
+ KBUILD_AFLAGS += -mno-relax
+ ifneq ($(LLVM_IAS),1)
+@@ -42,6 +43,7 @@ ifneq ($(LLVM_IAS),1)
+ KBUILD_AFLAGS += -Wa,-mno-relax
+ endif
+ endif
++endif
+
+ # ISA string setting
+ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
projects / thirdparty / kernel / stable-queue.git / commitdiff
