drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGE

The TILE_ADDR_RANGE register is not available on all platforms going
forward as it was deprecated and is being replaced by equivalent
registers within SoC MMIO space. While that doesn't happen, the
SG_TILE_ADDR_RANGE (base 0x1083a0) is still valid for all platforms
supported by xe. Use that instead.

BSpec: 59353, 54991
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patch.msgid.link/20251107-tile-addr-v1-1-a3014aadc2e7@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 2088256ad38199818c64d269030368c0b39a3645..917a088c28f24aebde08a611b3a82f228d81311c 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -101,7 +101,6 @@
 
 #define XE2_LMEM_CFG                           XE_REG(0x48b0)
 
-#define XEHP_TILE_ADDR_RANGE(_idx)             XE_REG_MCR(0x4900 + (_idx) * 4)
 #define XEHP_FLAT_CCS_BASE_ADDR                        XE_REG_MCR(0x4910)
 #define XEHP_FLAT_CCS_PTR                      REG_GENMASK(31, 8)
 

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 1926b4044314ece1d004be76e685dc5401612d43..ad93c57edd17c4d901c7bc5b9773a8ec55b9a6d1 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -40,6 +40,8 @@
 #define STOLEN_RESERVED                                XE_REG(0x1082c0)
 #define   WOPCM_SIZE_MASK                      REG_GENMASK64(9, 7)
 
+#define SG_TILE_ADDR_RANGE(_idx)               XE_REG(0x1083a0 + (_idx) * 4)
+
 #define MTL_RP_STATE_CAP                       XE_REG(0x138000)
 
 #define MTL_GT_RPA_FREQUENCY                   XE_REG(0x138008)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index b62a96f8ef9eb86913f531626d99245e19a267f0..56924f6a44ff28b0efd9b0c86173194c2f65712f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -274,7 +274,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
                *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
                *tile_offset = 0;
        } else {
-               reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
+               reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
                *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
                *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
        }