--- /dev/null
+From dfb3928065e46c572829f8ec4675898e42ddde56 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 30 Sep 2024 21:53:07 +0200
+Subject: accel/ivpu: Add auto selection logic for job scheduler
+
+From: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
+
+[ Upstream commit 436b67d6936b5658426e40d0df8f147239bc532b ]
+
+Add ivpu_fw_sched_mode_select() function that can select scheduling mode
+based on HW and FW versions. This prepares for a switch to HWS on
+selected platforms.
+
+Reviewed-by: Karol Wachowski <karol.wachowski@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240930195322.461209-17-jacek.lawrynowicz@linux.intel.com
+Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
+Stable-dep-of: 6c2b75404d33 ("accel/ivpu: Fix the NPU's DPU frequency calculation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/accel/ivpu/ivpu_drv.c | 6 +++---
+ drivers/accel/ivpu/ivpu_drv.h | 2 ++
+ drivers/accel/ivpu/ivpu_fw.c | 15 +++++++++++++--
+ drivers/accel/ivpu/ivpu_fw.h | 3 +++
+ drivers/accel/ivpu/ivpu_hw.h | 1 -
+ drivers/accel/ivpu/ivpu_hw_btrs.c | 2 --
+ drivers/accel/ivpu/ivpu_job.c | 14 +++++++-------
+ drivers/accel/ivpu/ivpu_sysfs.c | 24 ++++++++++++++++++++++++
+ 8 files changed, 52 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
+index 38b4158f52784..c929be956280e 100644
+--- a/drivers/accel/ivpu/ivpu_drv.c
++++ b/drivers/accel/ivpu/ivpu_drv.c
+@@ -54,9 +54,9 @@ u8 ivpu_pll_max_ratio = U8_MAX;
+ module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
+ MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
+
+-int ivpu_sched_mode;
++int ivpu_sched_mode = IVPU_SCHED_MODE_AUTO;
+ module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
+-MODULE_PARM_DESC(sched_mode, "Scheduler mode: 0 - Default scheduler, 1 - Force HW scheduler");
++MODULE_PARM_DESC(sched_mode, "Scheduler mode: -1 - Use default scheduler, 0 - Use OS scheduler, 1 - Use HW scheduler");
+
+ bool ivpu_disable_mmu_cont_pages;
+ module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
+@@ -347,7 +347,7 @@ static int ivpu_hw_sched_init(struct ivpu_device *vdev)
+ {
+ int ret = 0;
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+ ret = ivpu_jsm_hws_setup_priority_bands(vdev);
+ if (ret) {
+ ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
+diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h
+index 2b30cc2e9272e..9430a24994c32 100644
+--- a/drivers/accel/ivpu/ivpu_drv.h
++++ b/drivers/accel/ivpu/ivpu_drv.h
+@@ -57,6 +57,8 @@
+ #define IVPU_PLATFORM_FPGA 3
+ #define IVPU_PLATFORM_INVALID 8
+
++#define IVPU_SCHED_MODE_AUTO -1
++
+ #define IVPU_DBG_REG BIT(0)
+ #define IVPU_DBG_IRQ BIT(1)
+ #define IVPU_DBG_MMU BIT(2)
+diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
+index b2b6d89f06537..153037dc62c07 100644
+--- a/drivers/accel/ivpu/ivpu_fw.c
++++ b/drivers/accel/ivpu/ivpu_fw.c
+@@ -134,6 +134,15 @@ static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range
+ return true;
+ }
+
++static u32
++ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
++{
++ if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO)
++ return ivpu_sched_mode;
++
++ return VPU_SCHEDULING_MODE_OS;
++}
++
+ static int ivpu_fw_parse(struct ivpu_device *vdev)
+ {
+ struct ivpu_fw_info *fw = vdev->fw;
+@@ -215,8 +224,10 @@ static int ivpu_fw_parse(struct ivpu_device *vdev)
+
+ fw->dvfs_mode = 0;
+
++ fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
+ fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
+ fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
++ ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
+
+ if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
+ fw_hdr->ro_section_size,
+@@ -605,8 +616,8 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
+ boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
+ boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
+ boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
+- boot_params->vpu_scheduling_mode = vdev->hw->sched_mode;
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
++ boot_params->vpu_scheduling_mode = vdev->fw->sched_mode;
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
+ boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
+ boot_params->dvfs_mode = vdev->fw->dvfs_mode;
+ if (!IVPU_WA(disable_d0i3_msg))
+diff --git a/drivers/accel/ivpu/ivpu_fw.h b/drivers/accel/ivpu/ivpu_fw.h
+index 5e8eb608b70f1..1d0b2bd9d65cf 100644
+--- a/drivers/accel/ivpu/ivpu_fw.h
++++ b/drivers/accel/ivpu/ivpu_fw.h
+@@ -6,6 +6,8 @@
+ #ifndef __IVPU_FW_H__
+ #define __IVPU_FW_H__
+
++#include "vpu_jsm_api.h"
++
+ #define FW_VERSION_HEADER_SIZE SZ_4K
+ #define FW_VERSION_STR_SIZE SZ_256
+
+@@ -36,6 +38,7 @@ struct ivpu_fw_info {
+ u32 secondary_preempt_buf_size;
+ u64 read_only_addr;
+ u32 read_only_size;
++ u32 sched_mode;
+ };
+
+ int ivpu_fw_init(struct ivpu_device *vdev);
+diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h
+index a96a05b2acda9..fc4dbfc980c81 100644
+--- a/drivers/accel/ivpu/ivpu_hw.h
++++ b/drivers/accel/ivpu/ivpu_hw.h
+@@ -46,7 +46,6 @@ struct ivpu_hw_info {
+ u32 profiling_freq;
+ } pll;
+ u32 tile_fuse;
+- u32 sched_mode;
+ u32 sku;
+ u16 config;
+ int dma_bits;
+diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c
+index 745e5248803da..39c8fd51be32c 100644
+--- a/drivers/accel/ivpu/ivpu_hw_btrs.c
++++ b/drivers/accel/ivpu/ivpu_hw_btrs.c
+@@ -163,7 +163,6 @@ static int info_init_mtl(struct ivpu_device *vdev)
+ hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
+ hw->sku = BTRS_MTL_TILE_SKU_BOTH;
+ hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;
+- hw->sched_mode = ivpu_sched_mode;
+
+ return 0;
+ }
+@@ -178,7 +177,6 @@ static int info_init_lnl(struct ivpu_device *vdev)
+ if (ret)
+ return ret;
+
+- hw->sched_mode = ivpu_sched_mode;
+ hw->tile_fuse = tile_fuse_config;
+ hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
+
+diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_job.c
+index be2e2bf0f43f0..91f7f6f3ca675 100644
+--- a/drivers/accel/ivpu/ivpu_job.c
++++ b/drivers/accel/ivpu/ivpu_job.c
+@@ -37,7 +37,7 @@ static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
+ u64 secondary_size = ALIGN(vdev->fw->secondary_preempt_buf_size, PAGE_SIZE);
+ struct ivpu_addr_range range;
+
+- if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
++ if (vdev->fw->sched_mode != VPU_SCHEDULING_MODE_HW)
+ return 0;
+
+ range.start = vdev->hw->ranges.user.end - (primary_size * IVPU_NUM_CMDQS_PER_CTX);
+@@ -68,7 +68,7 @@ static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
+ static void ivpu_preemption_buffers_free(struct ivpu_device *vdev,
+ struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+ {
+- if (vdev->hw->sched_mode != VPU_SCHEDULING_MODE_HW)
++ if (vdev->fw->sched_mode != VPU_SCHEDULING_MODE_HW)
+ return;
+
+ drm_WARN_ON(&vdev->drm, !cmdq->primary_preempt_buf);
+@@ -149,7 +149,7 @@ static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *
+ struct ivpu_device *vdev = file_priv->vdev;
+ int ret;
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
+ ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->db_id, cmdq->db_id,
+ cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
+ else
+@@ -184,7 +184,7 @@ ivpu_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 eng
+ jobq_header->tail = 0;
+ wmb(); /* Flush WC buffer for jobq->header */
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+ ret = ivpu_hws_cmdq_init(file_priv, cmdq, engine, priority);
+ if (ret)
+ return ret;
+@@ -211,7 +211,7 @@ static int ivpu_cmdq_fini(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cm
+
+ cmdq->db_registered = false;
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW) {
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+ ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->db_id);
+ if (!ret)
+ ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->db_id);
+@@ -335,7 +335,7 @@ void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv)
+
+ ivpu_cmdq_fini_all(file_priv);
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_OS)
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_OS)
+ ivpu_jsm_context_release(vdev, file_priv->ctx.id);
+ }
+
+@@ -361,7 +361,7 @@ static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job)
+ if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION))
+ entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK;
+
+- if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW &&
++ if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW &&
+ (unlikely(!(ivpu_test_mode & IVPU_TEST_MODE_PREEMPTION_DISABLE)))) {
+ entry->primary_preempt_buf_addr = cmdq->primary_preempt_buf->vpu_addr;
+ entry->primary_preempt_buf_size = ivpu_bo_size(cmdq->primary_preempt_buf);
+diff --git a/drivers/accel/ivpu/ivpu_sysfs.c b/drivers/accel/ivpu/ivpu_sysfs.c
+index 913669f1786e8..616477fc17fa0 100644
+--- a/drivers/accel/ivpu/ivpu_sysfs.c
++++ b/drivers/accel/ivpu/ivpu_sysfs.c
+@@ -6,6 +6,8 @@
+ #include <linux/device.h>
+ #include <linux/err.h>
+
++#include "ivpu_drv.h"
++#include "ivpu_fw.h"
+ #include "ivpu_hw.h"
+ #include "ivpu_sysfs.h"
+
+@@ -39,8 +41,30 @@ npu_busy_time_us_show(struct device *dev, struct device_attribute *attr, char *b
+
+ static DEVICE_ATTR_RO(npu_busy_time_us);
+
++/**
++ * DOC: sched_mode
++ *
++ * The sched_mode is used to report current NPU scheduling mode.
++ *
++ * It returns following strings:
++ * - "HW" - Hardware Scheduler mode
++ * - "OS" - Operating System Scheduler mode
++ *
++ */
++static ssize_t
++sched_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ struct drm_device *drm = dev_get_drvdata(dev);
++ struct ivpu_device *vdev = to_ivpu_device(drm);
++
++ return sysfs_emit(buf, "%s\n", vdev->fw->sched_mode ? "HW" : "OS");
++}
++
++static DEVICE_ATTR_RO(sched_mode);
++
+ static struct attribute *ivpu_dev_attrs[] = {
+ &dev_attr_npu_busy_time_us.attr,
++ &dev_attr_sched_mode.attr,
+ NULL,
+ };
+
+--
+2.39.5
+
--- /dev/null
+From 1d0e5c31387a7d14b5bca07530b9a91b327fdf79 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Apr 2025 17:59:11 +0200
+Subject: accel/ivpu: Fix the NPU's DPU frequency calculation
+
+From: Andrzej Kacprowski <Andrzej.Kacprowski@intel.com>
+
+[ Upstream commit 6c2b75404d33caa46a582f2791a70f92232adb71 ]
+
+Fix the frequency returned to the user space by
+the DRM_IVPU_PARAM_CORE_CLOCK_RATE GET_PARAM IOCTL.
+The kernel driver returned CPU frequency for MTL and bare
+PLL frequency for LNL - this was inconsistent and incorrect
+for both platforms. With this fix the driver returns maximum
+frequency of the NPU data processing unit (DPU) for all HW
+generations. This is what user space always expected.
+
+Also do not set CPU frequency in boot params - the firmware
+does not use frequency passed from the driver, it was only
+used by the early pre-production firmware.
+With that we can remove CPU frequency calculation code.
+
+Show NPU frequency in FREQ_CHANGE interrupt when frequency
+tracking is enabled.
+
+Fixes: 8a27ad81f7d3 ("accel/ivpu: Split IP and buttress code")
+Cc: stable@vger.kernel.org # v6.11+
+Signed-off-by: Andrzej Kacprowski <Andrzej.Kacprowski@intel.com>
+Signed-off-by: Maciej Falkowski <maciej.falkowski@linux.intel.com>
+Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
+Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
+Link: https://lore.kernel.org/r/20250401155912.4049340-2-maciej.falkowski@linux.intel.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/accel/ivpu/ivpu_drv.c | 4 +-
+ drivers/accel/ivpu/ivpu_fw.c | 3 +-
+ drivers/accel/ivpu/ivpu_hw.h | 11 +--
+ drivers/accel/ivpu/ivpu_hw_btrs.c | 126 +++++++++++++-----------------
+ drivers/accel/ivpu/ivpu_hw_btrs.h | 6 +-
+ include/uapi/drm/ivpu_accel.h | 4 +-
+ 6 files changed, 66 insertions(+), 88 deletions(-)
+
+diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
+index c929be956280e..88df2cdc46b62 100644
+--- a/drivers/accel/ivpu/ivpu_drv.c
++++ b/drivers/accel/ivpu/ivpu_drv.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+ #include <linux/firmware.h>
+@@ -165,7 +165,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f
+ args->value = vdev->platform;
+ break;
+ case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
+- args->value = ivpu_hw_ratio_to_freq(vdev, vdev->hw->pll.max_ratio);
++ args->value = ivpu_hw_dpu_max_freq_get(vdev);
+ break;
+ case DRM_IVPU_PARAM_NUM_CONTEXTS:
+ args->value = ivpu_get_context_count(vdev);
+diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
+index 153037dc62c07..8a9395a2abb5d 100644
+--- a/drivers/accel/ivpu/ivpu_fw.c
++++ b/drivers/accel/ivpu/ivpu_fw.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+ #include <linux/firmware.h>
+@@ -556,7 +556,6 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
+
+ boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
+ boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
+- boot_params->frequency = ivpu_hw_pll_freq_get(vdev);
+
+ /*
+ * This param is a debug firmware feature. It switches default clock
+diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h
+index fc4dbfc980c81..1e85306bcd065 100644
+--- a/drivers/accel/ivpu/ivpu_hw.h
++++ b/drivers/accel/ivpu/ivpu_hw.h
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+ #ifndef __IVPU_HW_H__
+@@ -86,9 +86,9 @@ static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
+ return range->end - range->start;
+ }
+
+-static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
++static inline u32 ivpu_hw_dpu_max_freq_get(struct ivpu_device *vdev)
+ {
+- return ivpu_hw_btrs_ratio_to_freq(vdev, ratio);
++ return ivpu_hw_btrs_dpu_max_freq_get(vdev);
+ }
+
+ static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
+@@ -96,11 +96,6 @@ static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
+ ivpu_hw_ip_irq_clear(vdev);
+ }
+
+-static inline u32 ivpu_hw_pll_freq_get(struct ivpu_device *vdev)
+-{
+- return ivpu_hw_btrs_pll_freq_get(vdev);
+-}
+-
+ static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)
+ {
+ return vdev->hw->pll.profiling_freq;
+diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c
+index 39c8fd51be32c..2d88357b9a3a4 100644
+--- a/drivers/accel/ivpu/ivpu_hw_btrs.c
++++ b/drivers/accel/ivpu/ivpu_hw_btrs.c
+@@ -1,8 +1,10 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
++#include <linux/units.h>
++
+ #include "ivpu_drv.h"
+ #include "ivpu_hw.h"
+ #include "ivpu_hw_btrs.h"
+@@ -28,17 +30,13 @@
+
+ #define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
+
+-#define BTRS_MTL_WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_5_3)
+-#define BTRS_MTL_WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_1_TILE, MTL_PLL_RATIO_4_3)
+-#define BTRS_MTL_WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_5_3)
+-#define BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3)
+-#define BTRS_MTL_WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0)
+
+ #define PLL_CDYN_DEFAULT 0x80
+ #define PLL_EPP_DEFAULT 0x80
+ #define PLL_CONFIG_DEFAULT 0x0
+-#define PLL_SIMULATION_FREQ 10000000
+-#define PLL_REF_CLK_FREQ 50000000
++#define PLL_REF_CLK_FREQ 50000000ull
++#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
++
+ #define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC)
+ #define IDLE_TIMEOUT_US (5 * USEC_PER_MSEC)
+ #define TIMEOUT_US (150 * USEC_PER_MSEC)
+@@ -62,6 +60,8 @@
+ #define DCT_ENABLE 0x1
+ #define DCT_DISABLE 0x0
+
++static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio);
++
+ int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev)
+ {
+ REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK);
+@@ -162,7 +162,7 @@ static int info_init_mtl(struct ivpu_device *vdev)
+
+ hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
+ hw->sku = BTRS_MTL_TILE_SKU_BOTH;
+- hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;
++ hw->config = WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3);
+
+ return 0;
+ }
+@@ -344,8 +344,8 @@ int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable)
+
+ prepare_wp_request(vdev, &wp, enable);
+
+- ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
+- PLL_RATIO_TO_FREQ(wp.target), wp.cfg, wp.epp, wp.cdyn);
++ ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
++ pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);
+
+ ret = wp_request_send(vdev, &wp);
+ if (ret) {
+@@ -586,6 +586,39 @@ int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev)
+ return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
+ }
+
++static u32 pll_config_get_mtl(struct ivpu_device *vdev)
++{
++ return REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
++}
++
++static u32 pll_config_get_lnl(struct ivpu_device *vdev)
++{
++ return REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
++}
++
++static u32 pll_ratio_to_dpu_freq_mtl(u16 ratio)
++{
++ return (PLL_RATIO_TO_FREQ(ratio) * 2) / 3;
++}
++
++static u32 pll_ratio_to_dpu_freq_lnl(u16 ratio)
++{
++ return PLL_RATIO_TO_FREQ(ratio) / 2;
++}
++
++static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio)
++{
++ if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
++ return pll_ratio_to_dpu_freq_mtl(ratio);
++ else
++ return pll_ratio_to_dpu_freq_lnl(ratio);
++}
++
++u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev)
++{
++ return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio);
++}
++
+ /* Handler for IRQs from Buttress core (irqB) */
+ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
+ {
+@@ -595,9 +628,12 @@ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
+ if (!status)
+ return false;
+
+- if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status))
+- ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
+- REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL));
++ if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
++ u32 pll = pll_config_get_mtl(vdev);
++
++ ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
++ pll, pll_ratio_to_dpu_freq_mtl(pll) / HZ_PER_MHZ);
++ }
+
+ if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) {
+ ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
+@@ -647,8 +683,12 @@ bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq)
+ ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");
+ }
+
+- if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status))
+- ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ));
++ if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
++ u32 pll = pll_config_get_lnl(vdev);
++
++ ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
++ pll, pll_ratio_to_dpu_freq_lnl(pll) / HZ_PER_MHZ);
++ }
+
+ if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) {
+ ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
+@@ -731,60 +771,6 @@ void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 acti
+ REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val);
+ }
+
+-static u32 pll_ratio_to_freq_mtl(u32 ratio, u32 config)
+-{
+- u32 pll_clock = PLL_REF_CLK_FREQ * ratio;
+- u32 cpu_clock;
+-
+- if ((config & 0xff) == MTL_PLL_RATIO_4_3)
+- cpu_clock = pll_clock * 2 / 4;
+- else
+- cpu_clock = pll_clock * 2 / 5;
+-
+- return cpu_clock;
+-}
+-
+-u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
+-{
+- struct ivpu_hw_info *hw = vdev->hw;
+-
+- if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+- return pll_ratio_to_freq_mtl(ratio, hw->config);
+- else
+- return PLL_RATIO_TO_FREQ(ratio);
+-}
+-
+-static u32 pll_freq_get_mtl(struct ivpu_device *vdev)
+-{
+- u32 pll_curr_ratio;
+-
+- pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
+- pll_curr_ratio &= VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK;
+-
+- if (!ivpu_is_silicon(vdev))
+- return PLL_SIMULATION_FREQ;
+-
+- return pll_ratio_to_freq_mtl(pll_curr_ratio, vdev->hw->config);
+-}
+-
+-static u32 pll_freq_get_lnl(struct ivpu_device *vdev)
+-{
+- u32 pll_curr_ratio;
+-
+- pll_curr_ratio = REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
+- pll_curr_ratio &= VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK;
+-
+- return PLL_RATIO_TO_FREQ(pll_curr_ratio);
+-}
+-
+-u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev)
+-{
+- if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+- return pll_freq_get_mtl(vdev);
+- else
+- return pll_freq_get_lnl(vdev);
+-}
+-
+ u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev)
+ {
+ if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.h b/drivers/accel/ivpu/ivpu_hw_btrs.h
+index 04f14f50fed62..71792dab3c210 100644
+--- a/drivers/accel/ivpu/ivpu_hw_btrs.h
++++ b/drivers/accel/ivpu/ivpu_hw_btrs.h
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+ #ifndef __IVPU_HW_BTRS_H__
+@@ -13,7 +13,6 @@
+
+ #define PLL_PROFILING_FREQ_DEFAULT 38400000
+ #define PLL_PROFILING_FREQ_HIGH 400000000
+-#define PLL_RATIO_TO_FREQ(x) ((x) * PLL_REF_CLK_FREQ)
+
+ #define DCT_DEFAULT_ACTIVE_PERCENT 15u
+ #define DCT_PERIOD_US 35300u
+@@ -32,12 +31,11 @@ int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev);
+ void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev);
+ void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev);
+ void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev);
++u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev);
+ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq);
+ bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq);
+ int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable);
+ void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 dct_percent);
+-u32 ivpu_hw_btrs_pll_freq_get(struct ivpu_device *vdev);
+-u32 ivpu_hw_btrs_ratio_to_freq(struct ivpu_device *vdev, u32 ratio);
+ u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev);
+ u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev);
+ u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev);
+diff --git a/include/uapi/drm/ivpu_accel.h b/include/uapi/drm/ivpu_accel.h
+index 084fb529e1e96..13001da141c33 100644
+--- a/include/uapi/drm/ivpu_accel.h
++++ b/include/uapi/drm/ivpu_accel.h
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
+ /*
+- * Copyright (C) 2020-2024 Intel Corporation
++ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+ #ifndef __UAPI_IVPU_DRM_H__
+@@ -131,7 +131,7 @@ struct drm_ivpu_param {
+ * platform type when executing on a simulator or emulator (read-only)
+ *
+ * %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
+- * Current PLL frequency (read-only)
++ * Maximum frequency of the NPU data processing unit clock (read-only)
+ *
+ * %DRM_IVPU_PARAM_NUM_CONTEXTS:
+ * Maximum number of simultaneously existing contexts (read-only)
+--
+2.39.5
+
--- /dev/null
+From 15a0595c8e16942501b00d40f39d7ce08b7da7da Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 28 Feb 2025 11:08:50 +0530
+Subject: arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl
+ reg-masks
+
+From: Siddharth Vadapalli <s-vadapalli@ti.com>
+
+[ Upstream commit 38e7f9092efbbf2a4a67e4410b55b797f8d1e184 ]
+
+Commit under Fixes added the 'idle-states' property for SERDES4 lane muxes
+without defining the corresponding register offsets and masks for it in the
+'mux-reg-masks' property within the 'serdes_ln_ctrl' node.
+
+Fix this.
+
+Fixes: 7287d423f138 ("arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux")
+Cc: stable@vger.kernel.org
+Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
+Link: https://lore.kernel.org/r/20250228053850.506028-1-s-vadapalli@ti.com
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+index 7721852c1f68a..2475130ecad11 100644
+--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+@@ -84,7 +84,9 @@ serdes_ln_ctrl: mux-controller@4080 {
+ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
+ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+- <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
++ <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
++ <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
++ <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+--
+2.39.5
+
--- /dev/null
+From 7ad1bd8b99a3e7eb256a33d4b4856511115bf51e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 2 Sep 2024 17:56:49 +0530
+Subject: arm64: dts: ti: Refactor J784s4 SoC files to a common file
+
+From: Manorit Chawdhry <m-chawdhry@ti.com>
+
+[ Upstream commit 9cc161a4509c2fda7cbe35b4858b496cec03c5d0 ]
+
+Refactor J784s4 SoC files to a common file which uses the
+superset device to allow reuse in j742s2-evm which uses the subset part.
+
+Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
+Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
+Reviewed-by: Udit Kumar <u-kumar1@ti.com>
+Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-1-6a7aa2736797@ti.com
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+Stable-dep-of: 38e7f9092efb ("arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 148 +
+ .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2671 ++++++++++++++++
+ ...> k3-j784s4-j742s2-mcu-wakeup-common.dtsi} | 2 +-
+ ...i => k3-j784s4-j742s2-thermal-common.dtsi} | 0
+ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2847 +----------------
+ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 133 +-
+ 6 files changed, 2916 insertions(+), 2885 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
+ create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+ rename arch/arm64/boot/dts/ti/{k3-j784s4-mcu-wakeup.dtsi => k3-j784s4-j742s2-mcu-wakeup-common.dtsi} (99%)
+ rename arch/arm64/boot/dts/ti/{k3-j784s4-thermal.dtsi => k3-j784s4-j742s2-thermal-common.dtsi} (100%)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
+new file mode 100644
+index 0000000000000..1dceff119a470
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
+@@ -0,0 +1,148 @@
++// SPDX-License-Identifier: GPL-2.0-only OR MIT
++/*
++ * Device Tree Source for J784S4 and J742S2 SoC Family
++ *
++ * TRM (j784s4) (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
++ * TRM (j742s2): https://www.ti.com/lit/pdf/spruje3
++ *
++ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
++ *
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/soc/ti,sci_pm_domain.h>
++
++#include "k3-pinctrl.h"
++
++/ {
++ interrupt-parent = <&gic500>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ cache-level = <2>;
++ cache-unified;
++ cache-size = <0x200000>;
++ cache-line-size = <64>;
++ cache-sets = <1024>;
++ next-level-cache = <&msmc_l3>;
++ };
++
++ L2_1: l2-cache1 {
++ compatible = "cache";
++ cache-level = <2>;
++ cache-unified;
++ cache-size = <0x200000>;
++ cache-line-size = <64>;
++ cache-sets = <1024>;
++ next-level-cache = <&msmc_l3>;
++ };
++
++ msmc_l3: l3-cache0 {
++ compatible = "cache";
++ cache-level = <3>;
++ cache-unified;
++ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++
++ psci: psci {
++ compatible = "arm,psci-1.0";
++ method = "smc";
++ };
++ };
++
++ a72_timer0: timer-cl0-cpu0 {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a72-pmu";
++ /* Recommendation from GIC500 TRM Table A.3 */
++ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ cbass_main: bus@100000 {
++ bootph-all;
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
++ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
++ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
++ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
++ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
++ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
++ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
++ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
++ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
++ <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
++ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
++ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
++ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
++ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
++ <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
++ <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
++ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
++ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
++ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
++ <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
++ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
++ <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
++ <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
++ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
++ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
++ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
++
++ /* MCUSS_WKUP Range */
++ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
++ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
++ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
++ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
++ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
++ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
++ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
++ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
++ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
++ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
++ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
++ <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
++
++ cbass_mcu_wakeup: bus@28380000 {
++ bootph-all;
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
++ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
++ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
++ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
++ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
++ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
++ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
++ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
++ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
++ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
++ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
++ <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
++ };
++ };
++
++ thermal_zones: thermal-zones {
++ #include "k3-j784s4-j742s2-thermal-common.dtsi"
++ };
++};
++
++/* Now include peripherals from each bus segment */
++#include "k3-j784s4-j742s2-main-common.dtsi"
++#include "k3-j784s4-j742s2-mcu-wakeup-common.dtsi"
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+new file mode 100644
+index 0000000000000..7721852c1f68a
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+@@ -0,0 +1,2671 @@
++// SPDX-License-Identifier: GPL-2.0-only OR MIT
++/*
++ * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals
++ *
++ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
++ */
++
++#include <dt-bindings/mux/mux.h>
++#include <dt-bindings/phy/phy.h>
++#include <dt-bindings/phy/phy-ti.h>
++
++#include "k3-serdes.h"
++
++/ {
++ serdes_refclk: clock-serdes {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ /* To be enabled when serdes_wiz* is functional */
++ status = "disabled";
++ };
++};
++
++&cbass_main {
++ /*
++ * MSMC is configured by bootloaders and a runtime fixup is done in the
++ * DT for this node
++ */
++ msmc_ram: sram@70000000 {
++ compatible = "mmio-sram";
++ reg = <0x00 0x70000000 0x00 0x800000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x00 0x70000000 0x800000>;
++
++ atf-sram@0 {
++ reg = <0x00 0x20000>;
++ };
++
++ tifs-sram@1f0000 {
++ reg = <0x1f0000 0x10000>;
++ };
++
++ l3cache-sram@200000 {
++ reg = <0x200000 0x200000>;
++ };
++ };
++
++ scm_conf: bus@100000 {
++ compatible = "simple-bus";
++ reg = <0x00 0x00100000 0x00 0x1c000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x00 0x00100000 0x1c000>;
++
++ cpsw1_phy_gmii_sel: phy@4034 {
++ compatible = "ti,am654-phy-gmii-sel";
++ reg = <0x4034 0x4>;
++ #phy-cells = <1>;
++ };
++
++ cpsw0_phy_gmii_sel: phy@4044 {
++ compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
++ reg = <0x4044 0x20>;
++ #phy-cells = <1>;
++ ti,qsgmii-main-ports = <7>, <7>;
++ };
++
++ pcie0_ctrl: pcie0-ctrl@4070 {
++ compatible = "ti,j784s4-pcie-ctrl", "syscon";
++ reg = <0x4070 0x4>;
++ };
++
++ pcie1_ctrl: pcie1-ctrl@4074 {
++ compatible = "ti,j784s4-pcie-ctrl", "syscon";
++ reg = <0x4074 0x4>;
++ };
++
++ serdes_ln_ctrl: mux-controller@4080 {
++ compatible = "reg-mux";
++ reg = <0x00004080 0x30>;
++ #mux-control-cells = <1>;
++ mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
++ <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
++ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
++ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
++ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
++ <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
++ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
++ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
++ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
++ <J784S4_SERDES0_LANE3_USB>,
++ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
++ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
++ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
++ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
++ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
++ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
++ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
++ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
++ <J784S4_SERDES4_LANE0_EDP_LANE0>,
++ <J784S4_SERDES4_LANE1_EDP_LANE1>,
++ <J784S4_SERDES4_LANE2_EDP_LANE2>,
++ <J784S4_SERDES4_LANE3_EDP_LANE3>;
++ };
++
++ usb_serdes_mux: mux-controller@4000 {
++ compatible = "reg-mux";
++ reg = <0x4000 0x4>;
++ #mux-control-cells = <1>;
++ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
++ };
++
++ ehrpwm_tbclk: clock-controller@4140 {
++ compatible = "ti,am654-ehrpwm-tbclk";
++ reg = <0x4140 0x18>;
++ #clock-cells = <1>;
++ };
++
++ audio_refclk1: clock@82e4 {
++ compatible = "ti,am62-audio-refclk";
++ reg = <0x82e4 0x4>;
++ clocks = <&k3_clks 157 34>;
++ assigned-clocks = <&k3_clks 157 34>;
++ assigned-clock-parents = <&k3_clks 157 63>;
++ #clock-cells = <0>;
++ };
++ };
++
++ main_ehrpwm0: pwm@3000000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3000000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ main_ehrpwm1: pwm@3010000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3010000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ main_ehrpwm2: pwm@3020000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3020000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ main_ehrpwm3: pwm@3030000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3030000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ main_ehrpwm4: pwm@3040000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3040000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ main_ehrpwm5: pwm@3050000 {
++ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
++ reg = <0x00 0x3050000 0x00 0x100>;
++ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
++ clock-names = "tbclk", "fck";
++ power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ gic500: interrupt-controller@1800000 {
++ compatible = "arm,gic-v3";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
++ <0x00 0x01900000 0x00 0x100000>, /* GICR */
++ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
++ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
++ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
++
++ /* vcpumntirq: virtual CPU interface maintenance interrupt */
++ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
++
++ gic_its: msi-controller@1820000 {
++ compatible = "arm,gic-v3-its";
++ reg = <0x00 0x01820000 0x00 0x10000>;
++ socionext,synquacer-pre-its = <0x1000000 0x400000>;
++ msi-controller;
++ #msi-cells = <1>;
++ };
++ };
++
++ main_gpio_intr: interrupt-controller@a00000 {
++ compatible = "ti,sci-intr";
++ reg = <0x00 0x00a00000 0x00 0x800>;
++ ti,intr-trigger-type = <1>;
++ interrupt-controller;
++ interrupt-parent = <&gic500>;
++ #interrupt-cells = <1>;
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <10>;
++ ti,interrupt-ranges = <8 392 56>;
++ };
++
++ main_pmx0: pinctrl@11c000 {
++ compatible = "pinctrl-single";
++ /* Proxy 0 addressing */
++ reg = <0x00 0x11c000 0x00 0x120>;
++ #pinctrl-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <0xffffffff>;
++ };
++
++ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
++ main_timerio_input: pinctrl@104200 {
++ compatible = "pinctrl-single";
++ reg = <0x00 0x104200 0x00 0x50>;
++ #pinctrl-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <0x00000007>;
++ };
++
++ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
++ main_timerio_output: pinctrl@104280 {
++ compatible = "pinctrl-single";
++ reg = <0x00 0x104280 0x00 0x20>;
++ #pinctrl-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <0x0000001f>;
++ };
++
++ main_crypto: crypto@4e00000 {
++ compatible = "ti,j721e-sa2ul";
++ reg = <0x00 0x4e00000 0x00 0x1200>;
++ power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
++
++ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
++ <&main_udmap 0x4a41>;
++ dma-names = "tx", "rx1", "rx2";
++
++ rng: rng@4e10000 {
++ compatible = "inside-secure,safexcel-eip76";
++ reg = <0x00 0x4e10000 0x00 0x7d>;
++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++ };
++ };
++
++ main_timer0: timer@2400000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2400000 0x00 0x400>;
++ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 97 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 97 2>;
++ assigned-clock-parents = <&k3_clks 97 3>;
++ power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer1: timer@2410000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2410000 0x00 0x400>;
++ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 98 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 98 2>;
++ assigned-clock-parents = <&k3_clks 98 3>;
++ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer2: timer@2420000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2420000 0x00 0x400>;
++ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 99 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 99 2>;
++ assigned-clock-parents = <&k3_clks 99 3>;
++ power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer3: timer@2430000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2430000 0x00 0x400>;
++ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 100 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 100 2>;
++ assigned-clock-parents = <&k3_clks 100 3>;
++ power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer4: timer@2440000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2440000 0x00 0x400>;
++ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 101 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 101 2>;
++ assigned-clock-parents = <&k3_clks 101 3>;
++ power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer5: timer@2450000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2450000 0x00 0x400>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 102 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 102 2>;
++ assigned-clock-parents = <&k3_clks 102 3>;
++ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer6: timer@2460000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2460000 0x00 0x400>;
++ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 103 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 103 2>;
++ assigned-clock-parents = <&k3_clks 103 3>;
++ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer7: timer@2470000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2470000 0x00 0x400>;
++ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 104 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 104 2>;
++ assigned-clock-parents = <&k3_clks 104 3>;
++ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer8: timer@2480000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2480000 0x00 0x400>;
++ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 105 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 105 2>;
++ assigned-clock-parents = <&k3_clks 105 3>;
++ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer9: timer@2490000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2490000 0x00 0x400>;
++ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 106 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 106 2>;
++ assigned-clock-parents = <&k3_clks 106 3>;
++ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer10: timer@24a0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24a0000 0x00 0x400>;
++ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 107 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 107 2>;
++ assigned-clock-parents = <&k3_clks 107 3>;
++ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer11: timer@24b0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24b0000 0x00 0x400>;
++ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 108 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 108 2>;
++ assigned-clock-parents = <&k3_clks 108 3>;
++ power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer12: timer@24c0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24c0000 0x00 0x400>;
++ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 109 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 109 2>;
++ assigned-clock-parents = <&k3_clks 109 3>;
++ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer13: timer@24d0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24d0000 0x00 0x400>;
++ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 110 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 110 2>;
++ assigned-clock-parents = <&k3_clks 110 3>;
++ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer14: timer@24e0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24e0000 0x00 0x400>;
++ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 111 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 111 2>;
++ assigned-clock-parents = <&k3_clks 111 3>;
++ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer15: timer@24f0000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x24f0000 0x00 0x400>;
++ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 112 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 112 2>;
++ assigned-clock-parents = <&k3_clks 112 3>;
++ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer16: timer@2500000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2500000 0x00 0x400>;
++ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 113 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 113 2>;
++ assigned-clock-parents = <&k3_clks 113 3>;
++ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer17: timer@2510000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2510000 0x00 0x400>;
++ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 114 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 114 2>;
++ assigned-clock-parents = <&k3_clks 114 3>;
++ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer18: timer@2520000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2520000 0x00 0x400>;
++ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 115 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 115 2>;
++ assigned-clock-parents = <&k3_clks 115 3>;
++ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_timer19: timer@2530000 {
++ compatible = "ti,am654-timer";
++ reg = <0x00 0x2530000 0x00 0x400>;
++ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 116 2>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 116 2>;
++ assigned-clock-parents = <&k3_clks 116 3>;
++ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
++ ti,timer-pwm;
++ };
++
++ main_uart0: serial@2800000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02800000 0x00 0x200>;
++ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 146 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart1: serial@2810000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02810000 0x00 0x200>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 388 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart2: serial@2820000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02820000 0x00 0x200>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 389 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart3: serial@2830000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02830000 0x00 0x200>;
++ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 390 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart4: serial@2840000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02840000 0x00 0x200>;
++ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 391 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart5: serial@2850000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02850000 0x00 0x200>;
++ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 392 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart6: serial@2860000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02860000 0x00 0x200>;
++ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 393 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart7: serial@2870000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02870000 0x00 0x200>;
++ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 394 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart8: serial@2880000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02880000 0x00 0x200>;
++ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 395 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_uart9: serial@2890000 {
++ compatible = "ti,j721e-uart", "ti,am654-uart";
++ reg = <0x00 0x02890000 0x00 0x200>;
++ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 396 0>;
++ clock-names = "fclk";
++ power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_gpio0: gpio@600000 {
++ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
++ reg = <0x00 0x00600000 0x00 0x100>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&main_gpio_intr>;
++ interrupts = <145>, <146>, <147>, <148>, <149>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ ti,ngpio = <66>;
++ ti,davinci-gpio-unbanked = <0>;
++ power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 163 0>;
++ clock-names = "gpio";
++ status = "disabled";
++ };
++
++ main_gpio2: gpio@610000 {
++ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
++ reg = <0x00 0x00610000 0x00 0x100>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&main_gpio_intr>;
++ interrupts = <154>, <155>, <156>, <157>, <158>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ ti,ngpio = <66>;
++ ti,davinci-gpio-unbanked = <0>;
++ power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 164 0>;
++ clock-names = "gpio";
++ status = "disabled";
++ };
++
++ main_gpio4: gpio@620000 {
++ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
++ reg = <0x00 0x00620000 0x00 0x100>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&main_gpio_intr>;
++ interrupts = <163>, <164>, <165>, <166>, <167>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ ti,ngpio = <66>;
++ ti,davinci-gpio-unbanked = <0>;
++ power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 165 0>;
++ clock-names = "gpio";
++ status = "disabled";
++ };
++
++ main_gpio6: gpio@630000 {
++ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
++ reg = <0x00 0x00630000 0x00 0x100>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&main_gpio_intr>;
++ interrupts = <172>, <173>, <174>, <175>, <176>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ ti,ngpio = <66>;
++ ti,davinci-gpio-unbanked = <0>;
++ power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 166 0>;
++ clock-names = "gpio";
++ status = "disabled";
++ };
++
++ usbss0: usb@4104000 {
++ bootph-all;
++ compatible = "ti,j721e-usb";
++ reg = <0x00 0x4104000 0x00 0x100>;
++ dma-coherent;
++ power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
++ clock-names = "ref", "lpm";
++ assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
++ assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ status = "disabled"; /* Needs lane config */
++
++ usb0: usb@6000000 {
++ bootph-all;
++ compatible = "cdns,usb3";
++ reg = <0x00 0x6000000 0x00 0x10000>,
++ <0x00 0x6010000 0x00 0x10000>,
++ <0x00 0x6020000 0x00 0x10000>;
++ reg-names = "otg", "xhci", "dev";
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
++ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
++ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
++ interrupt-names = "host",
++ "peripheral",
++ "otg";
++ };
++ };
++
++ main_i2c0: i2c@2000000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02000000 0x00 0x100>;
++ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 270 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c1: i2c@2010000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02010000 0x00 0x100>;
++ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 271 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c2: i2c@2020000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02020000 0x00 0x100>;
++ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 272 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c3: i2c@2030000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02030000 0x00 0x100>;
++ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 273 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c4: i2c@2040000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02040000 0x00 0x100>;
++ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 274 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c5: i2c@2050000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02050000 0x00 0x100>;
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 275 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ main_i2c6: i2c@2060000 {
++ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
++ reg = <0x00 0x02060000 0x00 0x100>;
++ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 276 2>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ ti_csi2rx0: ticsi2rx@4500000 {
++ compatible = "ti,j721e-csi2rx-shim";
++ reg = <0x00 0x04500000 0x00 0x00001000>;
++ ranges;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dmas = <&main_bcdma_csi 0 0x4940 0>;
++ dma-names = "rx0";
++ power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++
++ cdns_csi2rx0: csi-bridge@4504000 {
++ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
++ reg = <0x00 0x04504000 0x00 0x00001000>;
++ clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
++ <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
++ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
++ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
++ phys = <&dphy0>;
++ phy-names = "dphy";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi0_port0: port@0 {
++ reg = <0>;
++ status = "disabled";
++ };
++
++ csi0_port1: port@1 {
++ reg = <1>;
++ status = "disabled";
++ };
++
++ csi0_port2: port@2 {
++ reg = <2>;
++ status = "disabled";
++ };
++
++ csi0_port3: port@3 {
++ reg = <3>;
++ status = "disabled";
++ };
++
++ csi0_port4: port@4 {
++ reg = <4>;
++ status = "disabled";
++ };
++ };
++ };
++ };
++
++ ti_csi2rx1: ticsi2rx@4510000 {
++ compatible = "ti,j721e-csi2rx-shim";
++ reg = <0x00 0x04510000 0x00 0x1000>;
++ ranges;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dmas = <&main_bcdma_csi 0 0x4960 0>;
++ dma-names = "rx0";
++ power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++
++ cdns_csi2rx1: csi-bridge@4514000 {
++ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
++ reg = <0x00 0x04514000 0x00 0x00001000>;
++ clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
++ <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
++ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
++ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
++ phys = <&dphy1>;
++ phy-names = "dphy";
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi1_port0: port@0 {
++ reg = <0>;
++ status = "disabled";
++ };
++
++ csi1_port1: port@1 {
++ reg = <1>;
++ status = "disabled";
++ };
++
++ csi1_port2: port@2 {
++ reg = <2>;
++ status = "disabled";
++ };
++
++ csi1_port3: port@3 {
++ reg = <3>;
++ status = "disabled";
++ };
++
++ csi1_port4: port@4 {
++ reg = <4>;
++ status = "disabled";
++ };
++ };
++ };
++ };
++
++ ti_csi2rx2: ticsi2rx@4520000 {
++ compatible = "ti,j721e-csi2rx-shim";
++ reg = <0x00 0x04520000 0x00 0x00001000>;
++ ranges;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dmas = <&main_bcdma_csi 0 0x4980 0>;
++ dma-names = "rx0";
++ power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++
++ cdns_csi2rx2: csi-bridge@4524000 {
++ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
++ reg = <0x00 0x04524000 0x00 0x00001000>;
++ clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
++ <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
++ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
++ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
++ phys = <&dphy2>;
++ phy-names = "dphy";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi2_port0: port@0 {
++ reg = <0>;
++ status = "disabled";
++ };
++
++ csi2_port1: port@1 {
++ reg = <1>;
++ status = "disabled";
++ };
++
++ csi2_port2: port@2 {
++ reg = <2>;
++ status = "disabled";
++ };
++
++ csi2_port3: port@3 {
++ reg = <3>;
++ status = "disabled";
++ };
++
++ csi2_port4: port@4 {
++ reg = <4>;
++ status = "disabled";
++ };
++ };
++ };
++ };
++
++ dphy0: phy@4580000 {
++ compatible = "cdns,dphy-rx";
++ reg = <0x00 0x04580000 0x00 0x00001100>;
++ #phy-cells = <0>;
++ power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ dphy1: phy@4590000 {
++ compatible = "cdns,dphy-rx";
++ reg = <0x00 0x04590000 0x00 0x00001100>;
++ #phy-cells = <0>;
++ power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ dphy2: phy@45a0000 {
++ compatible = "cdns,dphy-rx";
++ reg = <0x00 0x045a0000 0x00 0x00001100>;
++ #phy-cells = <0>;
++ power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ vpu0: video-codec@4210000 {
++ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
++ reg = <0x00 0x4210000 0x00 0x10000>;
++ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 241 2>;
++ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
++ };
++
++ vpu1: video-codec@4220000 {
++ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
++ reg = <0x00 0x4220000 0x00 0x10000>;
++ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&k3_clks 242 2>;
++ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
++ };
++
++ main_sdhci0: mmc@4f80000 {
++ compatible = "ti,j721e-sdhci-8bit";
++ reg = <0x00 0x04f80000 0x00 0x1000>,
++ <0x00 0x04f88000 0x00 0x400>;
++ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
++ clock-names = "clk_ahb", "clk_xin";
++ assigned-clocks = <&k3_clks 140 2>;
++ assigned-clock-parents = <&k3_clks 140 3>;
++ bus-width = <8>;
++ ti,otap-del-sel-legacy = <0x0>;
++ ti,otap-del-sel-mmc-hs = <0x0>;
++ ti,otap-del-sel-ddr52 = <0x6>;
++ ti,otap-del-sel-hs200 = <0x8>;
++ ti,otap-del-sel-hs400 = <0x5>;
++ ti,itap-del-sel-legacy = <0x10>;
++ ti,itap-del-sel-mmc-hs = <0xa>;
++ ti,strobe-sel = <0x77>;
++ ti,clkbuf-sel = <0x7>;
++ ti,trm-icp = <0x8>;
++ mmc-ddr-1_8v;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ dma-coherent;
++ status = "disabled";
++ };
++
++ main_sdhci1: mmc@4fb0000 {
++ compatible = "ti,j721e-sdhci-4bit";
++ reg = <0x00 0x04fb0000 0x00 0x1000>,
++ <0x00 0x04fb8000 0x00 0x400>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
++ clock-names = "clk_ahb", "clk_xin";
++ assigned-clocks = <&k3_clks 141 4>;
++ assigned-clock-parents = <&k3_clks 141 5>;
++ bus-width = <4>;
++ ti,otap-del-sel-legacy = <0x0>;
++ ti,otap-del-sel-sd-hs = <0x0>;
++ ti,otap-del-sel-sdr12 = <0xf>;
++ ti,otap-del-sel-sdr25 = <0xf>;
++ ti,otap-del-sel-sdr50 = <0xc>;
++ ti,otap-del-sel-sdr104 = <0x5>;
++ ti,otap-del-sel-ddr50 = <0xc>;
++ ti,itap-del-sel-legacy = <0x0>;
++ ti,itap-del-sel-sd-hs = <0x0>;
++ ti,itap-del-sel-sdr12 = <0x0>;
++ ti,itap-del-sel-sdr25 = <0x0>;
++ ti,itap-del-sel-ddr50 = <0x2>;
++ ti,clkbuf-sel = <0x7>;
++ ti,trm-icp = <0x8>;
++ dma-coherent;
++ status = "disabled";
++ };
++
++ pcie0_rc: pcie@2900000 {
++ compatible = "ti,j784s4-pcie-host";
++ reg = <0x00 0x02900000 0x00 0x1000>,
++ <0x00 0x02907000 0x00 0x400>,
++ <0x00 0x0d000000 0x00 0x00800000>,
++ <0x00 0x10000000 0x00 0x00001000>;
++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
++ interrupt-names = "link_state";
++ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
++ device_type = "pci";
++ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
++ max-link-speed = <3>;
++ num-lanes = <4>;
++ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 332 0>;
++ clock-names = "fck";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xff>;
++ vendor-id = <0x104c>;
++ device-id = <0xb012>;
++ msi-map = <0x0 &gic_its 0x0 0x10000>;
++ dma-coherent;
++ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
++ <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
++ status = "disabled";
++ };
++
++ pcie1_rc: pcie@2910000 {
++ compatible = "ti,j784s4-pcie-host";
++ reg = <0x00 0x02910000 0x00 0x1000>,
++ <0x00 0x02917000 0x00 0x400>,
++ <0x00 0x0d800000 0x00 0x00800000>,
++ <0x00 0x18000000 0x00 0x00001000>;
++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
++ interrupt-names = "link_state";
++ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
++ device_type = "pci";
++ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
++ max-link-speed = <3>;
++ num-lanes = <4>;
++ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 333 0>;
++ clock-names = "fck";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xff>;
++ vendor-id = <0x104c>;
++ device-id = <0xb012>;
++ msi-map = <0x0 &gic_its 0x10000 0x10000>;
++ dma-coherent;
++ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
++ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
++ status = "disabled";
++ };
++
++ serdes_wiz0: wiz@5060000 {
++ compatible = "ti,j784s4-wiz-10g";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
++ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
++ assigned-clocks = <&k3_clks 404 6>;
++ assigned-clock-parents = <&k3_clks 404 10>;
++ num-lanes = <4>;
++ #reset-cells = <1>;
++ #clock-cells = <1>;
++ ranges = <0x5060000 0x00 0x5060000 0x10000>;
++ status = "disabled";
++
++ serdes0: serdes@5060000 {
++ compatible = "ti,j721e-serdes-10g";
++ reg = <0x05060000 0x010000>;
++ reg-names = "torrent_phy";
++ resets = <&serdes_wiz0 0>;
++ reset-names = "torrent_reset";
++ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
++ clock-names = "refclk", "phy_en_refclk";
++ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
++ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
++ assigned-clock-parents = <&k3_clks 404 6>,
++ <&k3_clks 404 6>,
++ <&k3_clks 404 6>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <1>;
++ status = "disabled";
++ };
++ };
++
++ serdes_wiz1: wiz@5070000 {
++ compatible = "ti,j784s4-wiz-10g";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
++ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
++ assigned-clocks = <&k3_clks 405 6>;
++ assigned-clock-parents = <&k3_clks 405 10>;
++ num-lanes = <4>;
++ #reset-cells = <1>;
++ #clock-cells = <1>;
++ ranges = <0x05070000 0x00 0x05070000 0x10000>;
++ status = "disabled";
++
++ serdes1: serdes@5070000 {
++ compatible = "ti,j721e-serdes-10g";
++ reg = <0x05070000 0x010000>;
++ reg-names = "torrent_phy";
++ resets = <&serdes_wiz1 0>;
++ reset-names = "torrent_reset";
++ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
++ clock-names = "refclk", "phy_en_refclk";
++ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
++ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
++ assigned-clock-parents = <&k3_clks 405 6>,
++ <&k3_clks 405 6>,
++ <&k3_clks 405 6>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <1>;
++ status = "disabled";
++ };
++ };
++
++ serdes_wiz4: wiz@5050000 {
++ compatible = "ti,j784s4-wiz-10g";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
++ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
++ assigned-clocks = <&k3_clks 407 6>;
++ assigned-clock-parents = <&k3_clks 407 10>;
++ num-lanes = <4>;
++ #reset-cells = <1>;
++ #clock-cells = <1>;
++ ranges = <0x05050000 0x00 0x05050000 0x10000>,
++ <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
++ status = "disabled";
++
++ serdes4: serdes@5050000 {
++ /*
++ * Note: we also map DPTX PHY registers as the Torrent
++ * needs to manage those.
++ */
++ compatible = "ti,j721e-serdes-10g";
++ reg = <0x05050000 0x010000>,
++ <0x0a030a00 0x40>; /* DPTX PHY */
++ reg-names = "torrent_phy";
++ resets = <&serdes_wiz4 0>;
++ reset-names = "torrent_reset";
++ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
++ clock-names = "refclk", "phy_en_refclk";
++ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
++ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
++ assigned-clock-parents = <&k3_clks 407 6>,
++ <&k3_clks 407 6>,
++ <&k3_clks 407 6>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <1>;
++ status = "disabled";
++ };
++ };
++
++ main_navss: bus@30000000 {
++ bootph-all;
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
++ ti,sci-dev-id = <280>;
++ dma-coherent;
++ dma-ranges;
++
++ main_navss_intr: interrupt-controller@310e0000 {
++ compatible = "ti,sci-intr";
++ reg = <0x00 0x310e0000 0x00 0x4000>;
++ ti,intr-trigger-type = <4>;
++ interrupt-controller;
++ interrupt-parent = <&gic500>;
++ #interrupt-cells = <1>;
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <283>;
++ ti,interrupt-ranges = <0 64 64>,
++ <64 448 64>,
++ <128 672 64>;
++ };
++
++ main_udmass_inta: msi-controller@33d00000 {
++ compatible = "ti,sci-inta";
++ reg = <0x00 0x33d00000 0x00 0x100000>;
++ interrupt-controller;
++ #interrupt-cells = <0>;
++ interrupt-parent = <&main_navss_intr>;
++ msi-controller;
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <321>;
++ ti,interrupt-ranges = <0 0 256>;
++ ti,unmapped-event-sources = <&main_bcdma_csi>;
++ };
++
++ secure_proxy_main: mailbox@32c00000 {
++ bootph-all;
++ compatible = "ti,am654-secure-proxy";
++ #mbox-cells = <1>;
++ reg-names = "target_data", "rt", "scfg";
++ reg = <0x00 0x32c00000 0x00 0x100000>,
++ <0x00 0x32400000 0x00 0x100000>,
++ <0x00 0x32800000 0x00 0x100000>;
++ interrupt-names = "rx_011";
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ hwspinlock: hwlock@30e00000 {
++ compatible = "ti,am654-hwspinlock";
++ reg = <0x00 0x30e00000 0x00 0x1000>;
++ #hwlock-cells = <1>;
++ };
++
++ mailbox0_cluster0: mailbox@31f80000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f80000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster1: mailbox@31f81000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f81000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster2: mailbox@31f82000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f82000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster3: mailbox@31f83000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f83000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster4: mailbox@31f84000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f84000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster5: mailbox@31f85000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f85000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster6: mailbox@31f86000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f86000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster7: mailbox@31f87000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f87000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster8: mailbox@31f88000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f88000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster9: mailbox@31f89000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f89000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster10: mailbox@31f8a000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f8a000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox0_cluster11: mailbox@31f8b000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f8b000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster0: mailbox@31f90000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f90000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster1: mailbox@31f91000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f91000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster2: mailbox@31f92000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f92000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster3: mailbox@31f93000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f93000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster4: mailbox@31f94000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f94000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster5: mailbox@31f95000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f95000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster6: mailbox@31f96000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f96000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster7: mailbox@31f97000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f97000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster8: mailbox@31f98000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f98000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster9: mailbox@31f99000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f99000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster10: mailbox@31f9a000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f9a000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ mailbox1_cluster11: mailbox@31f9b000 {
++ compatible = "ti,am654-mailbox";
++ reg = <0x00 0x31f9b000 0x00 0x200>;
++ #mbox-cells = <1>;
++ ti,mbox-num-users = <4>;
++ ti,mbox-num-fifos = <16>;
++ interrupt-parent = <&main_navss_intr>;
++ status = "disabled";
++ };
++
++ main_ringacc: ringacc@3c000000 {
++ compatible = "ti,am654-navss-ringacc";
++ reg = <0x00 0x3c000000 0x00 0x400000>,
++ <0x00 0x38000000 0x00 0x400000>,
++ <0x00 0x31120000 0x00 0x100>,
++ <0x00 0x33000000 0x00 0x40000>,
++ <0x00 0x31080000 0x00 0x40000>;
++ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
++ ti,num-rings = <1024>;
++ ti,sci-rm-range-gp-rings = <0x1>;
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <315>;
++ msi-parent = <&main_udmass_inta>;
++ };
++
++ main_udmap: dma-controller@31150000 {
++ compatible = "ti,j721e-navss-main-udmap";
++ reg = <0x00 0x31150000 0x00 0x100>,
++ <0x00 0x34000000 0x00 0x80000>,
++ <0x00 0x35000000 0x00 0x200000>,
++ <0x00 0x30b00000 0x00 0x20000>,
++ <0x00 0x30c00000 0x00 0x8000>,
++ <0x00 0x30d00000 0x00 0x4000>;
++ reg-names = "gcfg", "rchanrt", "tchanrt",
++ "tchan", "rchan", "rflow";
++ msi-parent = <&main_udmass_inta>;
++ #dma-cells = <1>;
++
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <319>;
++ ti,ringacc = <&main_ringacc>;
++
++ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
++ <0x0f>, /* TX_HCHAN */
++ <0x10>; /* TX_UHCHAN */
++ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
++ <0x0b>, /* RX_HCHAN */
++ <0x0c>; /* RX_UHCHAN */
++ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
++ };
++
++ main_bcdma_csi: dma-controller@311a0000 {
++ compatible = "ti,j721s2-dmss-bcdma-csi";
++ reg = <0x00 0x311a0000 0x00 0x100>,
++ <0x00 0x35d00000 0x00 0x20000>,
++ <0x00 0x35c00000 0x00 0x10000>,
++ <0x00 0x35e00000 0x00 0x80000>;
++ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
++ msi-parent = <&main_udmass_inta>;
++ #dma-cells = <3>;
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <281>;
++ ti,sci-rm-range-rchan = <0x21>;
++ ti,sci-rm-range-tchan = <0x22>;
++ };
++
++ cpts@310d0000 {
++ compatible = "ti,j721e-cpts";
++ reg = <0x00 0x310d0000 0x00 0x400>;
++ reg-names = "cpts";
++ clocks = <&k3_clks 282 0>;
++ clock-names = "cpts";
++ assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
++ assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
++ interrupts-extended = <&main_navss_intr 391>;
++ interrupt-names = "cpts";
++ ti,cpts-periodic-outputs = <6>;
++ ti,cpts-ext-ts-inputs = <8>;
++ };
++ };
++
++ main_cpsw0: ethernet@c000000 {
++ compatible = "ti,j784s4-cpswxg-nuss";
++ reg = <0x00 0xc000000 0x00 0x200000>;
++ reg-names = "cpsw_nuss";
++ ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dma-coherent;
++ clocks = <&k3_clks 64 0>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
++
++ dmas = <&main_udmap 0xca00>,
++ <&main_udmap 0xca01>,
++ <&main_udmap 0xca02>,
++ <&main_udmap 0xca03>,
++ <&main_udmap 0xca04>,
++ <&main_udmap 0xca05>,
++ <&main_udmap 0xca06>,
++ <&main_udmap 0xca07>,
++ <&main_udmap 0x4a00>;
++ dma-names = "tx0", "tx1", "tx2", "tx3",
++ "tx4", "tx5", "tx6", "tx7",
++ "rx";
++
++ status = "disabled";
++
++ ethernet-ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ main_cpsw0_port1: port@1 {
++ reg = <1>;
++ label = "port1";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port2: port@2 {
++ reg = <2>;
++ label = "port2";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port3: port@3 {
++ reg = <3>;
++ label = "port3";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port4: port@4 {
++ reg = <4>;
++ label = "port4";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port5: port@5 {
++ reg = <5>;
++ label = "port5";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port6: port@6 {
++ reg = <6>;
++ label = "port6";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port7: port@7 {
++ reg = <7>;
++ label = "port7";
++ ti,mac-only;
++ status = "disabled";
++ };
++
++ main_cpsw0_port8: port@8 {
++ reg = <8>;
++ label = "port8";
++ ti,mac-only;
++ status = "disabled";
++ };
++ };
++
++ main_cpsw0_mdio: mdio@f00 {
++ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
++ reg = <0x00 0xf00 0x00 0x100>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 64 0>;
++ clock-names = "fck";
++ bus_freq = <1000000>;
++ status = "disabled";
++ };
++
++ cpts@3d000 {
++ compatible = "ti,am65-cpts";
++ reg = <0x00 0x3d000 0x00 0x400>;
++ clocks = <&k3_clks 64 3>;
++ clock-names = "cpts";
++ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "cpts";
++ ti,cpts-ext-ts-inputs = <4>;
++ ti,cpts-periodic-outputs = <2>;
++ };
++ };
++
++ main_cpsw1: ethernet@c200000 {
++ compatible = "ti,j721e-cpsw-nuss";
++ reg = <0x00 0xc200000 0x00 0x200000>;
++ reg-names = "cpsw_nuss";
++ ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dma-coherent;
++ clocks = <&k3_clks 62 0>;
++ clock-names = "fck";
++ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
++
++ dmas = <&main_udmap 0xc640>,
++ <&main_udmap 0xc641>,
++ <&main_udmap 0xc642>,
++ <&main_udmap 0xc643>,
++ <&main_udmap 0xc644>,
++ <&main_udmap 0xc645>,
++ <&main_udmap 0xc646>,
++ <&main_udmap 0xc647>,
++ <&main_udmap 0x4640>;
++ dma-names = "tx0", "tx1", "tx2", "tx3",
++ "tx4", "tx5", "tx6", "tx7",
++ "rx";
++
++ status = "disabled";
++
++ ethernet-ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ main_cpsw1_port1: port@1 {
++ reg = <1>;
++ label = "port1";
++ phys = <&cpsw1_phy_gmii_sel 1>;
++ ti,mac-only;
++ status = "disabled";
++ };
++ };
++
++ main_cpsw1_mdio: mdio@f00 {
++ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
++ reg = <0x00 0xf00 0x00 0x100>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&k3_clks 62 0>;
++ clock-names = "fck";
++ bus_freq = <1000000>;
++ status = "disabled";
++ };
++
++ cpts@3d000 {
++ compatible = "ti,am65-cpts";
++ reg = <0x00 0x3d000 0x00 0x400>;
++ clocks = <&k3_clks 62 3>;
++ clock-names = "cpts";
++ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "cpts";
++ ti,cpts-ext-ts-inputs = <4>;
++ ti,cpts-periodic-outputs = <2>;
++ };
++ };
++
++ main_mcan0: can@2701000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02701000 0x00 0x200>,
++ <0x00 0x02708000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan1: can@2711000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02711000 0x00 0x200>,
++ <0x00 0x02718000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan2: can@2721000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02721000 0x00 0x200>,
++ <0x00 0x02728000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan3: can@2731000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02731000 0x00 0x200>,
++ <0x00 0x02738000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan4: can@2741000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02741000 0x00 0x200>,
++ <0x00 0x02748000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan5: can@2751000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02751000 0x00 0x200>,
++ <0x00 0x02758000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan6: can@2761000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02761000 0x00 0x200>,
++ <0x00 0x02768000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan7: can@2771000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02771000 0x00 0x200>,
++ <0x00 0x02778000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan8: can@2781000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02781000 0x00 0x200>,
++ <0x00 0x02788000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan9: can@2791000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02791000 0x00 0x200>,
++ <0x00 0x02798000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan10: can@27a1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x027a1000 0x00 0x200>,
++ <0x00 0x027a8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan11: can@27b1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x027b1000 0x00 0x200>,
++ <0x00 0x027b8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan12: can@27c1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x027c1000 0x00 0x200>,
++ <0x00 0x027c8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan13: can@27d1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x027d1000 0x00 0x200>,
++ <0x00 0x027d8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan14: can@2681000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02681000 0x00 0x200>,
++ <0x00 0x02688000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan15: can@2691000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x02691000 0x00 0x200>,
++ <0x00 0x02698000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan16: can@26a1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x026a1000 0x00 0x200>,
++ <0x00 0x026a8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_mcan17: can@26b1000 {
++ compatible = "bosch,m_can";
++ reg = <0x00 0x026b1000 0x00 0x200>,
++ <0x00 0x026b8000 0x00 0x8000>;
++ reg-names = "m_can", "message_ram";
++ power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
++ clock-names = "hclk", "cclk";
++ interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
++ status = "disabled";
++ };
++
++ main_spi0: spi@2100000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02100000 0x00 0x400>;
++ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 376 1>;
++ status = "disabled";
++ };
++
++ main_spi1: spi@2110000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02110000 0x00 0x400>;
++ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 377 1>;
++ status = "disabled";
++ };
++
++ main_spi2: spi@2120000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02120000 0x00 0x400>;
++ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 378 1>;
++ status = "disabled";
++ };
++
++ main_spi3: spi@2130000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02130000 0x00 0x400>;
++ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 379 1>;
++ status = "disabled";
++ };
++
++ main_spi4: spi@2140000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02140000 0x00 0x400>;
++ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 380 1>;
++ status = "disabled";
++ };
++
++ main_spi5: spi@2150000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02150000 0x00 0x400>;
++ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 381 1>;
++ status = "disabled";
++ };
++
++ main_spi6: spi@2160000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02160000 0x00 0x400>;
++ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 382 1>;
++ status = "disabled";
++ };
++
++ main_spi7: spi@2170000 {
++ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
++ reg = <0x00 0x02170000 0x00 0x400>;
++ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 383 1>;
++ status = "disabled";
++ };
++
++ ufs_wrapper: ufs-wrapper@4e80000 {
++ compatible = "ti,j721e-ufs";
++ reg = <0x00 0x4e80000 0x00 0x100>;
++ power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 387 3>;
++ assigned-clocks = <&k3_clks 387 3>;
++ assigned-clock-parents = <&k3_clks 387 6>;
++ ranges;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ ufs@4e84000 {
++ compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
++ reg = <0x00 0x4e84000 0x00 0x10000>;
++ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++ freq-table-hz = <250000000 250000000>, <19200000 19200000>,
++ <19200000 19200000>;
++ clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>;
++ clock-names = "core_clk", "phy_clk", "ref_clk";
++ dma-coherent;
++ };
++ };
++
++ main_r5fss0: r5fss@5c00000 {
++ compatible = "ti,j721s2-r5fss";
++ ti,cluster-mode = <1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
++ <0x5d00000 0x00 0x5d00000 0x20000>;
++ power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
++
++ main_r5fss0_core0: r5f@5c00000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5c00000 0x00010000>,
++ <0x5c10000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <339>;
++ ti,sci-proc-ids = <0x06 0xff>;
++ resets = <&k3_reset 339 1>;
++ firmware-name = "j784s4-main-r5f0_0-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++
++ main_r5fss0_core1: r5f@5d00000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5d00000 0x00010000>,
++ <0x5d10000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <340>;
++ ti,sci-proc-ids = <0x07 0xff>;
++ resets = <&k3_reset 340 1>;
++ firmware-name = "j784s4-main-r5f0_1-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++ };
++
++ main_r5fss1: r5fss@5e00000 {
++ compatible = "ti,j721s2-r5fss";
++ ti,cluster-mode = <1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
++ <0x5f00000 0x00 0x5f00000 0x20000>;
++ power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
++
++ main_r5fss1_core0: r5f@5e00000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5e00000 0x00010000>,
++ <0x5e10000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <341>;
++ ti,sci-proc-ids = <0x08 0xff>;
++ resets = <&k3_reset 341 1>;
++ firmware-name = "j784s4-main-r5f1_0-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++
++ main_r5fss1_core1: r5f@5f00000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5f00000 0x00010000>,
++ <0x5f10000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <342>;
++ ti,sci-proc-ids = <0x09 0xff>;
++ resets = <&k3_reset 342 1>;
++ firmware-name = "j784s4-main-r5f1_1-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++ };
++
++ main_r5fss2: r5fss@5900000 {
++ compatible = "ti,j721s2-r5fss";
++ ti,cluster-mode = <1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x5900000 0x00 0x5900000 0x20000>,
++ <0x5a00000 0x00 0x5a00000 0x20000>;
++ power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
++
++ main_r5fss2_core0: r5f@5900000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5900000 0x00010000>,
++ <0x5910000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <343>;
++ ti,sci-proc-ids = <0x0a 0xff>;
++ resets = <&k3_reset 343 1>;
++ firmware-name = "j784s4-main-r5f2_0-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++
++ main_r5fss2_core1: r5f@5a00000 {
++ compatible = "ti,j721s2-r5f";
++ reg = <0x5a00000 0x00010000>,
++ <0x5a10000 0x00010000>;
++ reg-names = "atcm", "btcm";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <344>;
++ ti,sci-proc-ids = <0x0b 0xff>;
++ resets = <&k3_reset 344 1>;
++ firmware-name = "j784s4-main-r5f2_1-fw";
++ ti,atcm-enable = <1>;
++ ti,btcm-enable = <1>;
++ ti,loczrama = <1>;
++ };
++ };
++
++ c71_0: dsp@64800000 {
++ compatible = "ti,j721s2-c71-dsp";
++ reg = <0x00 0x64800000 0x00 0x00080000>,
++ <0x00 0x64e00000 0x00 0x0000c000>;
++ reg-names = "l2sram", "l1dram";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <30>;
++ ti,sci-proc-ids = <0x30 0xff>;
++ resets = <&k3_reset 30 1>;
++ firmware-name = "j784s4-c71_0-fw";
++ status = "disabled";
++ };
++
++ c71_1: dsp@65800000 {
++ compatible = "ti,j721s2-c71-dsp";
++ reg = <0x00 0x65800000 0x00 0x00080000>,
++ <0x00 0x65e00000 0x00 0x0000c000>;
++ reg-names = "l2sram", "l1dram";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <33>;
++ ti,sci-proc-ids = <0x31 0xff>;
++ resets = <&k3_reset 33 1>;
++ firmware-name = "j784s4-c71_1-fw";
++ status = "disabled";
++ };
++
++ c71_2: dsp@66800000 {
++ compatible = "ti,j721s2-c71-dsp";
++ reg = <0x00 0x66800000 0x00 0x00080000>,
++ <0x00 0x66e00000 0x00 0x0000c000>;
++ reg-names = "l2sram", "l1dram";
++ ti,sci = <&sms>;
++ ti,sci-dev-id = <37>;
++ ti,sci-proc-ids = <0x32 0xff>;
++ resets = <&k3_reset 37 1>;
++ firmware-name = "j784s4-c71_2-fw";
++ status = "disabled";
++ };
++
++ main_esm: esm@700000 {
++ compatible = "ti,j721e-esm";
++ reg = <0x00 0x700000 0x00 0x1000>;
++ ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>,
++ <695>;
++ bootph-pre-ram;
++ };
++
++ watchdog0: watchdog@2200000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2200000 0x00 0x100>;
++ clocks = <&k3_clks 348 0>;
++ power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 348 0>;
++ assigned-clock-parents = <&k3_clks 348 4>;
++ };
++
++ watchdog1: watchdog@2210000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2210000 0x00 0x100>;
++ clocks = <&k3_clks 349 0>;
++ power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 349 0>;
++ assigned-clock-parents = <&k3_clks 349 4>;
++ };
++
++ watchdog2: watchdog@2220000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2220000 0x00 0x100>;
++ clocks = <&k3_clks 350 0>;
++ power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 350 0>;
++ assigned-clock-parents = <&k3_clks 350 4>;
++ };
++
++ watchdog3: watchdog@2230000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2230000 0x00 0x100>;
++ clocks = <&k3_clks 351 0>;
++ power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 351 0>;
++ assigned-clock-parents = <&k3_clks 351 4>;
++ };
++
++ watchdog4: watchdog@2240000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2240000 0x00 0x100>;
++ clocks = <&k3_clks 352 0>;
++ power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 352 0>;
++ assigned-clock-parents = <&k3_clks 352 4>;
++ };
++
++ watchdog5: watchdog@2250000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2250000 0x00 0x100>;
++ clocks = <&k3_clks 353 0>;
++ power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 353 0>;
++ assigned-clock-parents = <&k3_clks 353 4>;
++ };
++
++ watchdog6: watchdog@2260000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2260000 0x00 0x100>;
++ clocks = <&k3_clks 354 0>;
++ power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 354 0>;
++ assigned-clock-parents = <&k3_clks 354 4>;
++ };
++
++ watchdog7: watchdog@2270000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2270000 0x00 0x100>;
++ clocks = <&k3_clks 355 0>;
++ power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 355 0>;
++ assigned-clock-parents = <&k3_clks 355 4>;
++ };
++
++ /*
++ * The following RTI instances are coupled with MCU R5Fs, c7x and
++ * GPU so keeping them reserved as these will be used by their
++ * respective firmware
++ */
++ watchdog8: watchdog@22f0000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x22f0000 0x00 0x100>;
++ clocks = <&k3_clks 360 0>;
++ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 360 0>;
++ assigned-clock-parents = <&k3_clks 360 4>;
++ /* reserved for GPU */
++ status = "reserved";
++ };
++
++ watchdog9: watchdog@2300000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2300000 0x00 0x100>;
++ clocks = <&k3_clks 356 0>;
++ power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 356 0>;
++ assigned-clock-parents = <&k3_clks 356 4>;
++ /* reserved for C7X_0 DSP */
++ status = "reserved";
++ };
++
++ watchdog10: watchdog@2310000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2310000 0x00 0x100>;
++ clocks = <&k3_clks 357 0>;
++ power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 357 0>;
++ assigned-clock-parents = <&k3_clks 357 4>;
++ /* reserved for C7X_1 DSP */
++ status = "reserved";
++ };
++
++ watchdog11: watchdog@2320000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2320000 0x00 0x100>;
++ clocks = <&k3_clks 358 0>;
++ power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 358 0>;
++ assigned-clock-parents = <&k3_clks 358 4>;
++ /* reserved for C7X_2 DSP */
++ status = "reserved";
++ };
++
++ watchdog12: watchdog@2330000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2330000 0x00 0x100>;
++ clocks = <&k3_clks 359 0>;
++ power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 359 0>;
++ assigned-clock-parents = <&k3_clks 359 4>;
++ /* reserved for C7X_3 DSP */
++ status = "reserved";
++ };
++
++ watchdog13: watchdog@23c0000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x23c0000 0x00 0x100>;
++ clocks = <&k3_clks 361 0>;
++ power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 361 0>;
++ assigned-clock-parents = <&k3_clks 361 4>;
++ /* reserved for MAIN_R5F0_0 */
++ status = "reserved";
++ };
++
++ watchdog14: watchdog@23d0000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x23d0000 0x00 0x100>;
++ clocks = <&k3_clks 362 0>;
++ power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 362 0>;
++ assigned-clock-parents = <&k3_clks 362 4>;
++ /* reserved for MAIN_R5F0_1 */
++ status = "reserved";
++ };
++
++ watchdog15: watchdog@23e0000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x23e0000 0x00 0x100>;
++ clocks = <&k3_clks 363 0>;
++ power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 363 0>;
++ assigned-clock-parents = <&k3_clks 363 4>;
++ /* reserved for MAIN_R5F1_0 */
++ status = "reserved";
++ };
++
++ watchdog16: watchdog@23f0000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x23f0000 0x00 0x100>;
++ clocks = <&k3_clks 364 0>;
++ power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 364 0>;
++ assigned-clock-parents = <&k3_clks 364 4>;
++ /* reserved for MAIN_R5F1_1 */
++ status = "reserved";
++ };
++
++ watchdog17: watchdog@2540000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2540000 0x00 0x100>;
++ clocks = <&k3_clks 365 0>;
++ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 365 0>;
++ assigned-clock-parents = <&k3_clks 366 4>;
++ /* reserved for MAIN_R5F2_0 */
++ status = "reserved";
++ };
++
++ watchdog18: watchdog@2550000 {
++ compatible = "ti,j7-rti-wdt";
++ reg = <0x00 0x2550000 0x00 0x100>;
++ clocks = <&k3_clks 366 0>;
++ power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;
++ assigned-clocks = <&k3_clks 366 0>;
++ assigned-clock-parents = <&k3_clks 366 4>;
++ /* reserved for MAIN_R5F2_1 */
++ status = "reserved";
++ };
++
++ mhdp: bridge@a000000 {
++ compatible = "ti,j721e-mhdp8546";
++ reg = <0x0 0xa000000 0x0 0x30a00>,
++ <0x0 0x4f40000 0x0 0x20>;
++ reg-names = "mhdptx", "j721e-intg";
++ clocks = <&k3_clks 217 11>;
++ interrupt-parent = <&gic500>;
++ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++
++ dp0_ports: ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ /* Remote-endpoints are on the boards so
++ * ports are defined in the platform dt file.
++ */
++ };
++ };
++
++ dss: dss@4a00000 {
++ compatible = "ti,j721e-dss";
++ reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
++ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
++ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
++ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
++ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
++ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
++ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
++ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
++ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
++ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
++ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
++ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
++ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
++ <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
++ <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
++ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
++ <0x00 0x04af0000 0x00 0x10000>; /* wb */
++ reg-names = "common_m", "common_s0",
++ "common_s1", "common_s2",
++ "vidl1", "vidl2","vid1","vid2",
++ "ovr1", "ovr2", "ovr3", "ovr4",
++ "vp1", "vp2", "vp3", "vp4",
++ "wb";
++ clocks = <&k3_clks 218 0>,
++ <&k3_clks 218 2>,
++ <&k3_clks 218 5>,
++ <&k3_clks 218 14>,
++ <&k3_clks 218 18>;
++ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
++ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
++ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "common_m",
++ "common_s0",
++ "common_s1",
++ "common_s2";
++ status = "disabled";
++
++ dss_ports: ports {
++ /* Ports that DSS drives are platform specific
++ * so they are defined in platform dt file.
++ */
++ };
++ };
++
++ mcasp0: mcasp@2b00000 {
++ compatible = "ti,am33xx-mcasp-audio";
++ reg = <0x00 0x02b00000 0x00 0x2000>,
++ <0x00 0x02b08000 0x00 0x1000>;
++ reg-names = "mpu","dat";
++ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "tx", "rx";
++ dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
++ dma-names = "tx", "rx";
++ clocks = <&k3_clks 265 0>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 265 0>;
++ assigned-clock-parents = <&k3_clks 265 1>;
++ power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ mcasp1: mcasp@2b10000 {
++ compatible = "ti,am33xx-mcasp-audio";
++ reg = <0x00 0x02b10000 0x00 0x2000>,
++ <0x00 0x02b18000 0x00 0x1000>;
++ reg-names = "mpu","dat";
++ interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "tx", "rx";
++ dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
++ dma-names = "tx", "rx";
++ clocks = <&k3_clks 266 0>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 266 0>;
++ assigned-clock-parents = <&k3_clks 266 1>;
++ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ mcasp2: mcasp@2b20000 {
++ compatible = "ti,am33xx-mcasp-audio";
++ reg = <0x00 0x02b20000 0x00 0x2000>,
++ <0x00 0x02b28000 0x00 0x1000>;
++ reg-names = "mpu","dat";
++ interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "tx", "rx";
++ dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
++ dma-names = "tx", "rx";
++ clocks = <&k3_clks 267 0>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 267 0>;
++ assigned-clock-parents = <&k3_clks 267 1>;
++ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ mcasp3: mcasp@2b30000 {
++ compatible = "ti,am33xx-mcasp-audio";
++ reg = <0x00 0x02b30000 0x00 0x2000>,
++ <0x00 0x02b38000 0x00 0x1000>;
++ reg-names = "mpu","dat";
++ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "tx", "rx";
++ dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
++ dma-names = "tx", "rx";
++ clocks = <&k3_clks 268 0>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 268 0>;
++ assigned-clock-parents = <&k3_clks 268 1>;
++ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++
++ mcasp4: mcasp@2b40000 {
++ compatible = "ti,am33xx-mcasp-audio";
++ reg = <0x00 0x02b40000 0x00 0x2000>,
++ <0x00 0x02b48000 0x00 0x1000>;
++ reg-names = "mpu","dat";
++ interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "tx", "rx";
++ dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
++ dma-names = "tx", "rx";
++ clocks = <&k3_clks 269 0>;
++ clock-names = "fck";
++ assigned-clocks = <&k3_clks 269 0>;
++ assigned-clock-parents = <&k3_clks 269 1>;
++ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
++ status = "disabled";
++ };
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+similarity index 99%
+rename from arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+rename to arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+index f603380fc91cf..cba8d0e64f2e6 100644
+--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0-only OR MIT
+ /*
+- * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
++ * Device Tree Source for J784S4 and J742S2 SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi
+similarity index 100%
+rename from arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi
+rename to arch/arm64/boot/dts/ti/k3-j784s4-j742s2-thermal-common.dtsi
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+index e73bb750b09ad..0160fe0da9838 100644
+--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+@@ -5,2781 +5,124 @@
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+-#include <dt-bindings/mux/mux.h>
+-#include <dt-bindings/phy/phy.h>
+-#include <dt-bindings/phy/phy-ti.h>
+-
+-#include "k3-serdes.h"
+-
+-/ {
+- serdes_refclk: clock-serdes {
+- #clock-cells = <0>;
+- compatible = "fixed-clock";
+- /* To be enabled when serdes_wiz* is functional */
+- status = "disabled";
+- };
+-};
+-
+-&cbass_main {
+- msmc_ram: sram@70000000 {
+- compatible = "mmio-sram";
+- reg = <0x00 0x70000000 0x00 0x800000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0x00 0x00 0x70000000 0x800000>;
+-
+- atf-sram@0 {
+- reg = <0x00 0x20000>;
+- };
+-
+- tifs-sram@1f0000 {
+- reg = <0x1f0000 0x10000>;
+- };
+-
+- l3cache-sram@200000 {
+- reg = <0x200000 0x200000>;
+- };
+- };
+-
+- scm_conf: bus@100000 {
+- compatible = "simple-bus";
+- reg = <0x00 0x00100000 0x00 0x1c000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0x00 0x00 0x00100000 0x1c000>;
+-
+- cpsw1_phy_gmii_sel: phy@4034 {
+- compatible = "ti,am654-phy-gmii-sel";
+- reg = <0x4034 0x4>;
+- #phy-cells = <1>;
+- };
+-
+- cpsw0_phy_gmii_sel: phy@4044 {
+- compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+- reg = <0x4044 0x20>;
+- #phy-cells = <1>;
+- ti,qsgmii-main-ports = <7>, <7>;
+- };
+-
+- pcie0_ctrl: pcie0-ctrl@4070 {
+- compatible = "ti,j784s4-pcie-ctrl", "syscon";
+- reg = <0x4070 0x4>;
+- };
+-
+- pcie1_ctrl: pcie1-ctrl@4074 {
+- compatible = "ti,j784s4-pcie-ctrl", "syscon";
+- reg = <0x4074 0x4>;
+- };
+-
+- pcie2_ctrl: pcie2-ctrl@4078 {
+- compatible = "ti,j784s4-pcie-ctrl", "syscon";
+- reg = <0x4078 0x4>;
+- };
+-
+- pcie3_ctrl: pcie3-ctrl@407c {
+- compatible = "ti,j784s4-pcie-ctrl", "syscon";
+- reg = <0x407c 0x4>;
+- };
+-
+- serdes_ln_ctrl: mux-controller@4080 {
+- compatible = "reg-mux";
+- reg = <0x00004080 0x30>;
+- #mux-control-cells = <1>;
+- mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+- <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
+- <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+- <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
+- <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+- <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
+- idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+- <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+- <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+- <J784S4_SERDES0_LANE3_USB>,
+- <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+- <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+- <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+- <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+- <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+- <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+- <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+- <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+- <J784S4_SERDES4_LANE0_EDP_LANE0>,
+- <J784S4_SERDES4_LANE1_EDP_LANE1>,
+- <J784S4_SERDES4_LANE2_EDP_LANE2>,
+- <J784S4_SERDES4_LANE3_EDP_LANE3>;
+- };
+-
+- usb_serdes_mux: mux-controller@4000 {
+- compatible = "reg-mux";
+- reg = <0x4000 0x4>;
+- #mux-control-cells = <1>;
+- mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
+- };
+-
+- ehrpwm_tbclk: clock-controller@4140 {
+- compatible = "ti,am654-ehrpwm-tbclk";
+- reg = <0x4140 0x18>;
+- #clock-cells = <1>;
+- };
+-
+- audio_refclk1: clock@82e4 {
+- compatible = "ti,am62-audio-refclk";
+- reg = <0x82e4 0x4>;
+- clocks = <&k3_clks 157 34>;
+- assigned-clocks = <&k3_clks 157 34>;
+- assigned-clock-parents = <&k3_clks 157 63>;
+- #clock-cells = <0>;
+- };
+- };
+-
+- main_ehrpwm0: pwm@3000000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3000000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- main_ehrpwm1: pwm@3010000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3010000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- main_ehrpwm2: pwm@3020000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3020000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- main_ehrpwm3: pwm@3030000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3030000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- main_ehrpwm4: pwm@3040000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3040000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- main_ehrpwm5: pwm@3050000 {
+- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+- reg = <0x00 0x3050000 0x00 0x100>;
+- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
+- clock-names = "tbclk", "fck";
+- power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- gic500: interrupt-controller@1800000 {
+- compatible = "arm,gic-v3";
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
+- #interrupt-cells = <3>;
+- interrupt-controller;
+- reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
+- <0x00 0x01900000 0x00 0x100000>, /* GICR */
+- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
+-
+- /* vcpumntirq: virtual CPU interface maintenance interrupt */
+- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-
+- gic_its: msi-controller@1820000 {
+- compatible = "arm,gic-v3-its";
+- reg = <0x00 0x01820000 0x00 0x10000>;
+- socionext,synquacer-pre-its = <0x1000000 0x400000>;
+- msi-controller;
+- #msi-cells = <1>;
+- };
+- };
+-
+- main_gpio_intr: interrupt-controller@a00000 {
+- compatible = "ti,sci-intr";
+- reg = <0x00 0x00a00000 0x00 0x800>;
+- ti,intr-trigger-type = <1>;
+- interrupt-controller;
+- interrupt-parent = <&gic500>;
+- #interrupt-cells = <1>;
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <10>;
+- ti,interrupt-ranges = <8 392 56>;
+- };
+-
+- main_pmx0: pinctrl@11c000 {
+- compatible = "pinctrl-single";
+- /* Proxy 0 addressing */
+- reg = <0x00 0x11c000 0x00 0x120>;
+- #pinctrl-cells = <1>;
+- pinctrl-single,register-width = <32>;
+- pinctrl-single,function-mask = <0xffffffff>;
+- };
+-
+- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+- main_timerio_input: pinctrl@104200 {
+- compatible = "pinctrl-single";
+- reg = <0x00 0x104200 0x00 0x50>;
+- #pinctrl-cells = <1>;
+- pinctrl-single,register-width = <32>;
+- pinctrl-single,function-mask = <0x00000007>;
+- };
+-
+- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+- main_timerio_output: pinctrl@104280 {
+- compatible = "pinctrl-single";
+- reg = <0x00 0x104280 0x00 0x20>;
+- #pinctrl-cells = <1>;
+- pinctrl-single,register-width = <32>;
+- pinctrl-single,function-mask = <0x0000001f>;
+- };
+-
+- main_crypto: crypto@4e00000 {
+- compatible = "ti,j721e-sa2ul";
+- reg = <0x00 0x4e00000 0x00 0x1200>;
+- power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+-
+- dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+- <&main_udmap 0x4a41>;
+- dma-names = "tx", "rx1", "rx2";
+-
+- rng: rng@4e10000 {
+- compatible = "inside-secure,safexcel-eip76";
+- reg = <0x00 0x4e10000 0x00 0x7d>;
+- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+- };
+- };
+-
+- main_timer0: timer@2400000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2400000 0x00 0x400>;
+- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 97 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 97 2>;
+- assigned-clock-parents = <&k3_clks 97 3>;
+- power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer1: timer@2410000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2410000 0x00 0x400>;
+- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 98 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 98 2>;
+- assigned-clock-parents = <&k3_clks 98 3>;
+- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer2: timer@2420000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2420000 0x00 0x400>;
+- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 99 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 99 2>;
+- assigned-clock-parents = <&k3_clks 99 3>;
+- power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer3: timer@2430000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2430000 0x00 0x400>;
+- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 100 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 100 2>;
+- assigned-clock-parents = <&k3_clks 100 3>;
+- power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer4: timer@2440000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2440000 0x00 0x400>;
+- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 101 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 101 2>;
+- assigned-clock-parents = <&k3_clks 101 3>;
+- power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer5: timer@2450000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2450000 0x00 0x400>;
+- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 102 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 102 2>;
+- assigned-clock-parents = <&k3_clks 102 3>;
+- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer6: timer@2460000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2460000 0x00 0x400>;
+- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 103 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 103 2>;
+- assigned-clock-parents = <&k3_clks 103 3>;
+- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer7: timer@2470000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2470000 0x00 0x400>;
+- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 104 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 104 2>;
+- assigned-clock-parents = <&k3_clks 104 3>;
+- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer8: timer@2480000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2480000 0x00 0x400>;
+- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 105 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 105 2>;
+- assigned-clock-parents = <&k3_clks 105 3>;
+- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer9: timer@2490000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2490000 0x00 0x400>;
+- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 106 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 106 2>;
+- assigned-clock-parents = <&k3_clks 106 3>;
+- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer10: timer@24a0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24a0000 0x00 0x400>;
+- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 107 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 107 2>;
+- assigned-clock-parents = <&k3_clks 107 3>;
+- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer11: timer@24b0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24b0000 0x00 0x400>;
+- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 108 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 108 2>;
+- assigned-clock-parents = <&k3_clks 108 3>;
+- power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer12: timer@24c0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24c0000 0x00 0x400>;
+- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 109 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 109 2>;
+- assigned-clock-parents = <&k3_clks 109 3>;
+- power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer13: timer@24d0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24d0000 0x00 0x400>;
+- interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 110 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 110 2>;
+- assigned-clock-parents = <&k3_clks 110 3>;
+- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer14: timer@24e0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24e0000 0x00 0x400>;
+- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 111 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 111 2>;
+- assigned-clock-parents = <&k3_clks 111 3>;
+- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer15: timer@24f0000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x24f0000 0x00 0x400>;
+- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 112 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 112 2>;
+- assigned-clock-parents = <&k3_clks 112 3>;
+- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer16: timer@2500000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2500000 0x00 0x400>;
+- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 113 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 113 2>;
+- assigned-clock-parents = <&k3_clks 113 3>;
+- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer17: timer@2510000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2510000 0x00 0x400>;
+- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 114 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 114 2>;
+- assigned-clock-parents = <&k3_clks 114 3>;
+- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer18: timer@2520000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2520000 0x00 0x400>;
+- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 115 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 115 2>;
+- assigned-clock-parents = <&k3_clks 115 3>;
+- power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_timer19: timer@2530000 {
+- compatible = "ti,am654-timer";
+- reg = <0x00 0x2530000 0x00 0x400>;
+- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 116 2>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 116 2>;
+- assigned-clock-parents = <&k3_clks 116 3>;
+- power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
+- ti,timer-pwm;
+- };
+-
+- main_uart0: serial@2800000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02800000 0x00 0x200>;
+- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 146 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart1: serial@2810000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02810000 0x00 0x200>;
+- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 388 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart2: serial@2820000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02820000 0x00 0x200>;
+- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 389 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart3: serial@2830000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02830000 0x00 0x200>;
+- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 390 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart4: serial@2840000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02840000 0x00 0x200>;
+- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 391 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart5: serial@2850000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02850000 0x00 0x200>;
+- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 392 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart6: serial@2860000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02860000 0x00 0x200>;
+- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 393 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart7: serial@2870000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02870000 0x00 0x200>;
+- interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 394 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart8: serial@2880000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02880000 0x00 0x200>;
+- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 395 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_uart9: serial@2890000 {
+- compatible = "ti,j721e-uart", "ti,am654-uart";
+- reg = <0x00 0x02890000 0x00 0x200>;
+- interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 396 0>;
+- clock-names = "fclk";
+- power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_gpio0: gpio@600000 {
+- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+- reg = <0x00 0x00600000 0x00 0x100>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- interrupt-parent = <&main_gpio_intr>;
+- interrupts = <145>, <146>, <147>, <148>, <149>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- ti,ngpio = <66>;
+- ti,davinci-gpio-unbanked = <0>;
+- power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 163 0>;
+- clock-names = "gpio";
+- status = "disabled";
+- };
+-
+- main_gpio2: gpio@610000 {
+- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+- reg = <0x00 0x00610000 0x00 0x100>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- interrupt-parent = <&main_gpio_intr>;
+- interrupts = <154>, <155>, <156>, <157>, <158>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- ti,ngpio = <66>;
+- ti,davinci-gpio-unbanked = <0>;
+- power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 164 0>;
+- clock-names = "gpio";
+- status = "disabled";
+- };
+-
+- main_gpio4: gpio@620000 {
+- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+- reg = <0x00 0x00620000 0x00 0x100>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- interrupt-parent = <&main_gpio_intr>;
+- interrupts = <163>, <164>, <165>, <166>, <167>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- ti,ngpio = <66>;
+- ti,davinci-gpio-unbanked = <0>;
+- power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 165 0>;
+- clock-names = "gpio";
+- status = "disabled";
+- };
+-
+- main_gpio6: gpio@630000 {
+- compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+- reg = <0x00 0x00630000 0x00 0x100>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- interrupt-parent = <&main_gpio_intr>;
+- interrupts = <172>, <173>, <174>, <175>, <176>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- ti,ngpio = <66>;
+- ti,davinci-gpio-unbanked = <0>;
+- power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 166 0>;
+- clock-names = "gpio";
+- status = "disabled";
+- };
+-
+- usbss0: usb@4104000 {
+- bootph-all;
+- compatible = "ti,j721e-usb";
+- reg = <0x00 0x4104000 0x00 0x100>;
+- dma-coherent;
+- power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
+- clock-names = "ref", "lpm";
+- assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
+- assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
+-
+- status = "disabled"; /* Needs lane config */
+-
+- usb0: usb@6000000 {
+- bootph-all;
+- compatible = "cdns,usb3";
+- reg = <0x00 0x6000000 0x00 0x10000>,
+- <0x00 0x6010000 0x00 0x10000>,
+- <0x00 0x6020000 0x00 0x10000>;
+- reg-names = "otg", "xhci", "dev";
+- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+- interrupt-names = "host",
+- "peripheral",
+- "otg";
+- };
+- };
+-
+- main_i2c0: i2c@2000000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02000000 0x00 0x100>;
+- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 270 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c1: i2c@2010000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02010000 0x00 0x100>;
+- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 271 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c2: i2c@2020000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02020000 0x00 0x100>;
+- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 272 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c3: i2c@2030000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02030000 0x00 0x100>;
+- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 273 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c4: i2c@2040000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02040000 0x00 0x100>;
+- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 274 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c5: i2c@2050000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02050000 0x00 0x100>;
+- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 275 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- main_i2c6: i2c@2060000 {
+- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+- reg = <0x00 0x02060000 0x00 0x100>;
+- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 276 2>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- ti_csi2rx0: ticsi2rx@4500000 {
+- compatible = "ti,j721e-csi2rx-shim";
+- reg = <0x00 0x04500000 0x00 0x00001000>;
+- ranges;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- dmas = <&main_bcdma_csi 0 0x4940 0>;
+- dma-names = "rx0";
+- power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+-
+- cdns_csi2rx0: csi-bridge@4504000 {
+- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+- reg = <0x00 0x04504000 0x00 0x00001000>;
+- clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
+- <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
+- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+- phys = <&dphy0>;
+- phy-names = "dphy";
+-
+- ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- csi0_port0: port@0 {
+- reg = <0>;
+- status = "disabled";
+- };
+-
+- csi0_port1: port@1 {
+- reg = <1>;
+- status = "disabled";
+- };
+-
+- csi0_port2: port@2 {
+- reg = <2>;
+- status = "disabled";
+- };
+-
+- csi0_port3: port@3 {
+- reg = <3>;
+- status = "disabled";
+- };
+-
+- csi0_port4: port@4 {
+- reg = <4>;
+- status = "disabled";
+- };
+- };
+- };
+- };
+-
+- ti_csi2rx1: ticsi2rx@4510000 {
+- compatible = "ti,j721e-csi2rx-shim";
+- reg = <0x00 0x04510000 0x00 0x1000>;
+- ranges;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- dmas = <&main_bcdma_csi 0 0x4960 0>;
+- dma-names = "rx0";
+- power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+-
+- cdns_csi2rx1: csi-bridge@4514000 {
+- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+- reg = <0x00 0x04514000 0x00 0x00001000>;
+- clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
+- <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
+- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+- phys = <&dphy1>;
+- phy-names = "dphy";
+- ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- csi1_port0: port@0 {
+- reg = <0>;
+- status = "disabled";
+- };
+-
+- csi1_port1: port@1 {
+- reg = <1>;
+- status = "disabled";
+- };
+-
+- csi1_port2: port@2 {
+- reg = <2>;
+- status = "disabled";
+- };
+-
+- csi1_port3: port@3 {
+- reg = <3>;
+- status = "disabled";
+- };
+-
+- csi1_port4: port@4 {
+- reg = <4>;
+- status = "disabled";
+- };
+- };
+- };
+- };
+-
+- ti_csi2rx2: ticsi2rx@4520000 {
+- compatible = "ti,j721e-csi2rx-shim";
+- reg = <0x00 0x04520000 0x00 0x00001000>;
+- ranges;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- dmas = <&main_bcdma_csi 0 0x4980 0>;
+- dma-names = "rx0";
+- power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+-
+- cdns_csi2rx2: csi-bridge@4524000 {
+- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+- reg = <0x00 0x04524000 0x00 0x00001000>;
+- clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
+- <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
+- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+- phys = <&dphy2>;
+- phy-names = "dphy";
+-
+- ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- csi2_port0: port@0 {
+- reg = <0>;
+- status = "disabled";
+- };
+-
+- csi2_port1: port@1 {
+- reg = <1>;
+- status = "disabled";
+- };
+-
+- csi2_port2: port@2 {
+- reg = <2>;
+- status = "disabled";
+- };
+-
+- csi2_port3: port@3 {
+- reg = <3>;
+- status = "disabled";
+- };
+-
+- csi2_port4: port@4 {
+- reg = <4>;
+- status = "disabled";
+- };
+- };
+- };
+- };
+-
+- dphy0: phy@4580000 {
+- compatible = "cdns,dphy-rx";
+- reg = <0x00 0x04580000 0x00 0x00001100>;
+- #phy-cells = <0>;
+- power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- dphy1: phy@4590000 {
+- compatible = "cdns,dphy-rx";
+- reg = <0x00 0x04590000 0x00 0x00001100>;
+- #phy-cells = <0>;
+- power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- dphy2: phy@45a0000 {
+- compatible = "cdns,dphy-rx";
+- reg = <0x00 0x045a0000 0x00 0x00001100>;
+- #phy-cells = <0>;
+- power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+- };
+-
+- vpu0: video-codec@4210000 {
+- compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+- reg = <0x00 0x4210000 0x00 0x10000>;
+- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 241 2>;
+- power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+- };
+-
+- vpu1: video-codec@4220000 {
+- compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+- reg = <0x00 0x4220000 0x00 0x10000>;
+- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&k3_clks 242 2>;
+- power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+- };
+-
+- main_sdhci0: mmc@4f80000 {
+- compatible = "ti,j721e-sdhci-8bit";
+- reg = <0x00 0x04f80000 0x00 0x1000>,
+- <0x00 0x04f88000 0x00 0x400>;
+- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+- power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
+- clock-names = "clk_ahb", "clk_xin";
+- assigned-clocks = <&k3_clks 140 2>;
+- assigned-clock-parents = <&k3_clks 140 3>;
+- bus-width = <8>;
+- ti,otap-del-sel-legacy = <0x0>;
+- ti,otap-del-sel-mmc-hs = <0x0>;
+- ti,otap-del-sel-ddr52 = <0x6>;
+- ti,otap-del-sel-hs200 = <0x8>;
+- ti,otap-del-sel-hs400 = <0x5>;
+- ti,itap-del-sel-legacy = <0x10>;
+- ti,itap-del-sel-mmc-hs = <0xa>;
+- ti,strobe-sel = <0x77>;
+- ti,clkbuf-sel = <0x7>;
+- ti,trm-icp = <0x8>;
+- mmc-ddr-1_8v;
+- mmc-hs200-1_8v;
+- mmc-hs400-1_8v;
+- dma-coherent;
+- status = "disabled";
+- };
+-
+- main_sdhci1: mmc@4fb0000 {
+- compatible = "ti,j721e-sdhci-4bit";
+- reg = <0x00 0x04fb0000 0x00 0x1000>,
+- <0x00 0x04fb8000 0x00 0x400>;
+- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
+- clock-names = "clk_ahb", "clk_xin";
+- assigned-clocks = <&k3_clks 141 4>;
+- assigned-clock-parents = <&k3_clks 141 5>;
+- bus-width = <4>;
+- ti,otap-del-sel-legacy = <0x0>;
+- ti,otap-del-sel-sd-hs = <0x0>;
+- ti,otap-del-sel-sdr12 = <0xf>;
+- ti,otap-del-sel-sdr25 = <0xf>;
+- ti,otap-del-sel-sdr50 = <0xc>;
+- ti,otap-del-sel-sdr104 = <0x5>;
+- ti,otap-del-sel-ddr50 = <0xc>;
+- ti,itap-del-sel-legacy = <0x0>;
+- ti,itap-del-sel-sd-hs = <0x0>;
+- ti,itap-del-sel-sdr12 = <0x0>;
+- ti,itap-del-sel-sdr25 = <0x0>;
+- ti,itap-del-sel-ddr50 = <0x2>;
+- ti,clkbuf-sel = <0x7>;
+- ti,trm-icp = <0x8>;
+- dma-coherent;
+- status = "disabled";
+- };
+-
+- pcie0_rc: pcie@2900000 {
+- compatible = "ti,j784s4-pcie-host";
+- reg = <0x00 0x02900000 0x00 0x1000>,
+- <0x00 0x02907000 0x00 0x400>,
+- <0x00 0x0d000000 0x00 0x00800000>,
+- <0x00 0x10000000 0x00 0x00001000>;
+- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+- interrupt-names = "link_state";
+- interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+- device_type = "pci";
+- ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+- max-link-speed = <3>;
+- num-lanes = <4>;
+- power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 332 0>;
+- clock-names = "fck";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- bus-range = <0x0 0xff>;
+- vendor-id = <0x104c>;
+- device-id = <0xb012>;
+- msi-map = <0x0 &gic_its 0x0 0x10000>;
+- dma-coherent;
+- ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+- <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+- status = "disabled";
+- };
+-
+- pcie1_rc: pcie@2910000 {
+- compatible = "ti,j784s4-pcie-host";
+- reg = <0x00 0x02910000 0x00 0x1000>,
+- <0x00 0x02917000 0x00 0x400>,
+- <0x00 0x0d800000 0x00 0x00800000>,
+- <0x00 0x18000000 0x00 0x00001000>;
+- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+- interrupt-names = "link_state";
+- interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+- device_type = "pci";
+- ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+- max-link-speed = <3>;
+- num-lanes = <4>;
+- power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 333 0>;
+- clock-names = "fck";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- bus-range = <0x0 0xff>;
+- vendor-id = <0x104c>;
+- device-id = <0xb012>;
+- msi-map = <0x0 &gic_its 0x10000 0x10000>;
+- dma-coherent;
+- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+- status = "disabled";
+- };
+-
+- pcie2_rc: pcie@2920000 {
+- compatible = "ti,j784s4-pcie-host";
+- reg = <0x00 0x02920000 0x00 0x1000>,
+- <0x00 0x02927000 0x00 0x400>,
+- <0x00 0x0e000000 0x00 0x00800000>,
+- <0x44 0x00000000 0x00 0x00001000>;
+- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+- interrupt-names = "link_state";
+- interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+- device_type = "pci";
+- ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+- max-link-speed = <3>;
+- num-lanes = <2>;
+- power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 334 0>;
+- clock-names = "fck";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- bus-range = <0x0 0xff>;
+- vendor-id = <0x104c>;
+- device-id = <0xb012>;
+- msi-map = <0x0 &gic_its 0x20000 0x10000>;
+- dma-coherent;
+- ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
+- <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
+- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+- status = "disabled";
+- };
+-
+- pcie3_rc: pcie@2930000 {
+- compatible = "ti,j784s4-pcie-host";
+- reg = <0x00 0x02930000 0x00 0x1000>,
+- <0x00 0x02937000 0x00 0x400>,
+- <0x00 0x0e800000 0x00 0x00800000>,
+- <0x44 0x10000000 0x00 0x00001000>;
+- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+- interrupt-names = "link_state";
+- interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+- device_type = "pci";
+- ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+- max-link-speed = <3>;
+- num-lanes = <2>;
+- power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 335 0>;
+- clock-names = "fck";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- bus-range = <0x0 0xff>;
+- vendor-id = <0x104c>;
+- device-id = <0xb012>;
+- msi-map = <0x0 &gic_its 0x30000 0x10000>;
+- dma-coherent;
+- ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
+- <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
+- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+- status = "disabled";
+- };
+-
+- serdes_wiz0: wiz@5060000 {
+- compatible = "ti,j784s4-wiz-10g";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
+- clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+- assigned-clocks = <&k3_clks 404 6>;
+- assigned-clock-parents = <&k3_clks 404 10>;
+- num-lanes = <4>;
+- #reset-cells = <1>;
+- #clock-cells = <1>;
+- ranges = <0x5060000 0x00 0x5060000 0x10000>;
+- status = "disabled";
+-
+- serdes0: serdes@5060000 {
+- compatible = "ti,j721e-serdes-10g";
+- reg = <0x05060000 0x010000>;
+- reg-names = "torrent_phy";
+- resets = <&serdes_wiz0 0>;
+- reset-names = "torrent_reset";
+- clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+- clock-names = "refclk", "phy_en_refclk";
+- assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+- <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+- assigned-clock-parents = <&k3_clks 404 6>,
+- <&k3_clks 404 6>,
+- <&k3_clks 404 6>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <1>;
+- status = "disabled";
+- };
+- };
+-
+- serdes_wiz1: wiz@5070000 {
+- compatible = "ti,j784s4-wiz-10g";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
+- clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+- assigned-clocks = <&k3_clks 405 6>;
+- assigned-clock-parents = <&k3_clks 405 10>;
+- num-lanes = <4>;
+- #reset-cells = <1>;
+- #clock-cells = <1>;
+- ranges = <0x05070000 0x00 0x05070000 0x10000>;
+- status = "disabled";
+-
+- serdes1: serdes@5070000 {
+- compatible = "ti,j721e-serdes-10g";
+- reg = <0x05070000 0x010000>;
+- reg-names = "torrent_phy";
+- resets = <&serdes_wiz1 0>;
+- reset-names = "torrent_reset";
+- clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+- clock-names = "refclk", "phy_en_refclk";
+- assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+- <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+- assigned-clock-parents = <&k3_clks 405 6>,
+- <&k3_clks 405 6>,
+- <&k3_clks 405 6>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <1>;
+- status = "disabled";
+- };
+- };
+-
+- serdes_wiz2: wiz@5020000 {
+- compatible = "ti,j784s4-wiz-10g";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
+- clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+- assigned-clocks = <&k3_clks 406 6>;
+- assigned-clock-parents = <&k3_clks 406 10>;
+- num-lanes = <4>;
+- #reset-cells = <1>;
+- #clock-cells = <1>;
+- ranges = <0x05020000 0x00 0x05020000 0x10000>;
+- status = "disabled";
+-
+- serdes2: serdes@5020000 {
+- compatible = "ti,j721e-serdes-10g";
+- reg = <0x05020000 0x010000>;
+- reg-names = "torrent_phy";
+- resets = <&serdes_wiz2 0>;
+- reset-names = "torrent_reset";
+- clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+- clock-names = "refclk", "phy_en_refclk";
+- assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+- <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+- assigned-clock-parents = <&k3_clks 406 6>,
+- <&k3_clks 406 6>,
+- <&k3_clks 406 6>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <1>;
+- status = "disabled";
+- };
+- };
+-
+- serdes_wiz4: wiz@5050000 {
+- compatible = "ti,j784s4-wiz-10g";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
+- clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+- assigned-clocks = <&k3_clks 407 6>;
+- assigned-clock-parents = <&k3_clks 407 10>;
+- num-lanes = <4>;
+- #reset-cells = <1>;
+- #clock-cells = <1>;
+- ranges = <0x05050000 0x00 0x05050000 0x10000>,
+- <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+- status = "disabled";
+-
+- serdes4: serdes@5050000 {
+- /*
+- * Note: we also map DPTX PHY registers as the Torrent
+- * needs to manage those.
+- */
+- compatible = "ti,j721e-serdes-10g";
+- reg = <0x05050000 0x010000>,
+- <0x0a030a00 0x40>; /* DPTX PHY */
+- reg-names = "torrent_phy";
+- resets = <&serdes_wiz4 0>;
+- reset-names = "torrent_reset";
+- clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+- clock-names = "refclk", "phy_en_refclk";
+- assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+- <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+- <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+- assigned-clock-parents = <&k3_clks 407 6>,
+- <&k3_clks 407 6>,
+- <&k3_clks 407 6>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <1>;
+- status = "disabled";
+- };
+- };
+-
+- main_navss: bus@30000000 {
+- bootph-all;
+- compatible = "simple-bus";
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+- ti,sci-dev-id = <280>;
+- dma-coherent;
+- dma-ranges;
+-
+- main_navss_intr: interrupt-controller@310e0000 {
+- compatible = "ti,sci-intr";
+- reg = <0x00 0x310e0000 0x00 0x4000>;
+- ti,intr-trigger-type = <4>;
+- interrupt-controller;
+- interrupt-parent = <&gic500>;
+- #interrupt-cells = <1>;
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <283>;
+- ti,interrupt-ranges = <0 64 64>,
+- <64 448 64>,
+- <128 672 64>;
+- };
+-
+- main_udmass_inta: msi-controller@33d00000 {
+- compatible = "ti,sci-inta";
+- reg = <0x00 0x33d00000 0x00 0x100000>;
+- interrupt-controller;
+- #interrupt-cells = <0>;
+- interrupt-parent = <&main_navss_intr>;
+- msi-controller;
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <321>;
+- ti,interrupt-ranges = <0 0 256>;
+- ti,unmapped-event-sources = <&main_bcdma_csi>;
+- };
+-
+- secure_proxy_main: mailbox@32c00000 {
+- bootph-all;
+- compatible = "ti,am654-secure-proxy";
+- #mbox-cells = <1>;
+- reg-names = "target_data", "rt", "scfg";
+- reg = <0x00 0x32c00000 0x00 0x100000>,
+- <0x00 0x32400000 0x00 0x100000>,
+- <0x00 0x32800000 0x00 0x100000>;
+- interrupt-names = "rx_011";
+- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- hwspinlock: hwlock@30e00000 {
+- compatible = "ti,am654-hwspinlock";
+- reg = <0x00 0x30e00000 0x00 0x1000>;
+- #hwlock-cells = <1>;
+- };
+-
+- mailbox0_cluster0: mailbox@31f80000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f80000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster1: mailbox@31f81000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f81000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster2: mailbox@31f82000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f82000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster3: mailbox@31f83000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f83000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster4: mailbox@31f84000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f84000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster5: mailbox@31f85000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f85000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster6: mailbox@31f86000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f86000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster7: mailbox@31f87000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f87000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster8: mailbox@31f88000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f88000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster9: mailbox@31f89000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f89000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster10: mailbox@31f8a000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f8a000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox0_cluster11: mailbox@31f8b000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f8b000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster0: mailbox@31f90000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f90000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster1: mailbox@31f91000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f91000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster2: mailbox@31f92000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f92000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster3: mailbox@31f93000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f93000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster4: mailbox@31f94000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f94000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster5: mailbox@31f95000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f95000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster6: mailbox@31f96000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f96000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster7: mailbox@31f97000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f97000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster8: mailbox@31f98000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f98000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster9: mailbox@31f99000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f99000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster10: mailbox@31f9a000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f9a000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- mailbox1_cluster11: mailbox@31f9b000 {
+- compatible = "ti,am654-mailbox";
+- reg = <0x00 0x31f9b000 0x00 0x200>;
+- #mbox-cells = <1>;
+- ti,mbox-num-users = <4>;
+- ti,mbox-num-fifos = <16>;
+- interrupt-parent = <&main_navss_intr>;
+- status = "disabled";
+- };
+-
+- main_ringacc: ringacc@3c000000 {
+- compatible = "ti,am654-navss-ringacc";
+- reg = <0x00 0x3c000000 0x00 0x400000>,
+- <0x00 0x38000000 0x00 0x400000>,
+- <0x00 0x31120000 0x00 0x100>,
+- <0x00 0x33000000 0x00 0x40000>,
+- <0x00 0x31080000 0x00 0x40000>;
+- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+- ti,num-rings = <1024>;
+- ti,sci-rm-range-gp-rings = <0x1>;
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <315>;
+- msi-parent = <&main_udmass_inta>;
+- };
+-
+- main_udmap: dma-controller@31150000 {
+- compatible = "ti,j721e-navss-main-udmap";
+- reg = <0x00 0x31150000 0x00 0x100>,
+- <0x00 0x34000000 0x00 0x80000>,
+- <0x00 0x35000000 0x00 0x200000>,
+- <0x00 0x30b00000 0x00 0x20000>,
+- <0x00 0x30c00000 0x00 0x8000>,
+- <0x00 0x30d00000 0x00 0x4000>;
+- reg-names = "gcfg", "rchanrt", "tchanrt",
+- "tchan", "rchan", "rflow";
+- msi-parent = <&main_udmass_inta>;
+- #dma-cells = <1>;
+-
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <319>;
+- ti,ringacc = <&main_ringacc>;
+-
+- ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+- <0x0f>, /* TX_HCHAN */
+- <0x10>; /* TX_UHCHAN */
+- ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+- <0x0b>, /* RX_HCHAN */
+- <0x0c>; /* RX_UHCHAN */
+- ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+- };
+-
+- main_bcdma_csi: dma-controller@311a0000 {
+- compatible = "ti,j721s2-dmss-bcdma-csi";
+- reg = <0x00 0x311a0000 0x00 0x100>,
+- <0x00 0x35d00000 0x00 0x20000>,
+- <0x00 0x35c00000 0x00 0x10000>,
+- <0x00 0x35e00000 0x00 0x80000>;
+- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+- msi-parent = <&main_udmass_inta>;
+- #dma-cells = <3>;
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <281>;
+- ti,sci-rm-range-rchan = <0x21>;
+- ti,sci-rm-range-tchan = <0x22>;
+- };
+-
+- cpts@310d0000 {
+- compatible = "ti,j721e-cpts";
+- reg = <0x00 0x310d0000 0x00 0x400>;
+- reg-names = "cpts";
+- clocks = <&k3_clks 282 0>;
+- clock-names = "cpts";
+- assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
+- assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
+- interrupts-extended = <&main_navss_intr 391>;
+- interrupt-names = "cpts";
+- ti,cpts-periodic-outputs = <6>;
+- ti,cpts-ext-ts-inputs = <8>;
+- };
+- };
+-
+- main_cpsw0: ethernet@c000000 {
+- compatible = "ti,j784s4-cpswxg-nuss";
+- reg = <0x00 0xc000000 0x00 0x200000>;
+- reg-names = "cpsw_nuss";
+- ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- dma-coherent;
+- clocks = <&k3_clks 64 0>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+-
+- dmas = <&main_udmap 0xca00>,
+- <&main_udmap 0xca01>,
+- <&main_udmap 0xca02>,
+- <&main_udmap 0xca03>,
+- <&main_udmap 0xca04>,
+- <&main_udmap 0xca05>,
+- <&main_udmap 0xca06>,
+- <&main_udmap 0xca07>,
+- <&main_udmap 0x4a00>;
+- dma-names = "tx0", "tx1", "tx2", "tx3",
+- "tx4", "tx5", "tx6", "tx7",
+- "rx";
+-
+- status = "disabled";
+-
+- ethernet-ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- main_cpsw0_port1: port@1 {
+- reg = <1>;
+- label = "port1";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port2: port@2 {
+- reg = <2>;
+- label = "port2";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port3: port@3 {
+- reg = <3>;
+- label = "port3";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port4: port@4 {
+- reg = <4>;
+- label = "port4";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port5: port@5 {
+- reg = <5>;
+- label = "port5";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port6: port@6 {
+- reg = <6>;
+- label = "port6";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port7: port@7 {
+- reg = <7>;
+- label = "port7";
+- ti,mac-only;
+- status = "disabled";
+- };
+-
+- main_cpsw0_port8: port@8 {
+- reg = <8>;
+- label = "port8";
+- ti,mac-only;
+- status = "disabled";
+- };
+- };
+-
+- main_cpsw0_mdio: mdio@f00 {
+- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+- reg = <0x00 0xf00 0x00 0x100>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 64 0>;
+- clock-names = "fck";
+- bus_freq = <1000000>;
+- status = "disabled";
+- };
+-
+- cpts@3d000 {
+- compatible = "ti,am65-cpts";
+- reg = <0x00 0x3d000 0x00 0x400>;
+- clocks = <&k3_clks 64 3>;
+- clock-names = "cpts";
+- interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "cpts";
+- ti,cpts-ext-ts-inputs = <4>;
+- ti,cpts-periodic-outputs = <2>;
+- };
+- };
+-
+- main_cpsw1: ethernet@c200000 {
+- compatible = "ti,j721e-cpsw-nuss";
+- reg = <0x00 0xc200000 0x00 0x200000>;
+- reg-names = "cpsw_nuss";
+- ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- dma-coherent;
+- clocks = <&k3_clks 62 0>;
+- clock-names = "fck";
+- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+-
+- dmas = <&main_udmap 0xc640>,
+- <&main_udmap 0xc641>,
+- <&main_udmap 0xc642>,
+- <&main_udmap 0xc643>,
+- <&main_udmap 0xc644>,
+- <&main_udmap 0xc645>,
+- <&main_udmap 0xc646>,
+- <&main_udmap 0xc647>,
+- <&main_udmap 0x4640>;
+- dma-names = "tx0", "tx1", "tx2", "tx3",
+- "tx4", "tx5", "tx6", "tx7",
+- "rx";
+-
+- status = "disabled";
+-
+- ethernet-ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- main_cpsw1_port1: port@1 {
+- reg = <1>;
+- label = "port1";
+- phys = <&cpsw1_phy_gmii_sel 1>;
+- ti,mac-only;
+- status = "disabled";
+- };
+- };
+-
+- main_cpsw1_mdio: mdio@f00 {
+- compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+- reg = <0x00 0xf00 0x00 0x100>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks = <&k3_clks 62 0>;
+- clock-names = "fck";
+- bus_freq = <1000000>;
+- status = "disabled";
+- };
+-
+- cpts@3d000 {
+- compatible = "ti,am65-cpts";
+- reg = <0x00 0x3d000 0x00 0x400>;
+- clocks = <&k3_clks 62 3>;
+- clock-names = "cpts";
+- interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "cpts";
+- ti,cpts-ext-ts-inputs = <4>;
+- ti,cpts-periodic-outputs = <2>;
+- };
+- };
+-
+- main_mcan0: can@2701000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02701000 0x00 0x200>,
+- <0x00 0x02708000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan1: can@2711000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02711000 0x00 0x200>,
+- <0x00 0x02718000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan2: can@2721000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02721000 0x00 0x200>,
+- <0x00 0x02728000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan3: can@2731000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02731000 0x00 0x200>,
+- <0x00 0x02738000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan4: can@2741000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02741000 0x00 0x200>,
+- <0x00 0x02748000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan5: can@2751000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02751000 0x00 0x200>,
+- <0x00 0x02758000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan6: can@2761000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02761000 0x00 0x200>,
+- <0x00 0x02768000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan7: can@2771000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02771000 0x00 0x200>,
+- <0x00 0x02778000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan8: can@2781000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02781000 0x00 0x200>,
+- <0x00 0x02788000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan9: can@2791000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02791000 0x00 0x200>,
+- <0x00 0x02798000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan10: can@27a1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x027a1000 0x00 0x200>,
+- <0x00 0x027a8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan11: can@27b1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x027b1000 0x00 0x200>,
+- <0x00 0x027b8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan12: can@27c1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x027c1000 0x00 0x200>,
+- <0x00 0x027c8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan13: can@27d1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x027d1000 0x00 0x200>,
+- <0x00 0x027d8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan14: can@2681000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02681000 0x00 0x200>,
+- <0x00 0x02688000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan15: can@2691000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x02691000 0x00 0x200>,
+- <0x00 0x02698000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan16: can@26a1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x026a1000 0x00 0x200>,
+- <0x00 0x026a8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_mcan17: can@26b1000 {
+- compatible = "bosch,m_can";
+- reg = <0x00 0x026b1000 0x00 0x200>,
+- <0x00 0x026b8000 0x00 0x8000>;
+- reg-names = "m_can", "message_ram";
+- power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
+- clock-names = "hclk", "cclk";
+- interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+- status = "disabled";
+- };
+-
+- main_spi0: spi@2100000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02100000 0x00 0x400>;
+- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 376 1>;
+- status = "disabled";
+- };
+-
+- main_spi1: spi@2110000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02110000 0x00 0x400>;
+- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 377 1>;
+- status = "disabled";
+- };
+-
+- main_spi2: spi@2120000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02120000 0x00 0x400>;
+- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 378 1>;
+- status = "disabled";
+- };
+-
+- main_spi3: spi@2130000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02130000 0x00 0x400>;
+- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 379 1>;
+- status = "disabled";
+- };
+-
+- main_spi4: spi@2140000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02140000 0x00 0x400>;
+- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 380 1>;
+- status = "disabled";
+- };
+-
+- main_spi5: spi@2150000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02150000 0x00 0x400>;
+- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 381 1>;
+- status = "disabled";
+- };
+-
+- main_spi6: spi@2160000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02160000 0x00 0x400>;
+- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 382 1>;
+- status = "disabled";
+- };
+-
+- main_spi7: spi@2170000 {
+- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+- reg = <0x00 0x02170000 0x00 0x400>;
+- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 383 1>;
+- status = "disabled";
+- };
+-
+- ufs_wrapper: ufs-wrapper@4e80000 {
+- compatible = "ti,j721e-ufs";
+- reg = <0x00 0x4e80000 0x00 0x100>;
+- power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
+- clocks = <&k3_clks 387 3>;
+- assigned-clocks = <&k3_clks 387 3>;
+- assigned-clock-parents = <&k3_clks 387 6>;
+- ranges;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- status = "disabled";
+-
+- ufs@4e84000 {
+- compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
+- reg = <0x00 0x4e84000 0x00 0x10000>;
+- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+- freq-table-hz = <250000000 250000000>, <19200000 19200000>,
+- <19200000 19200000>;
+- clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>;
+- clock-names = "core_clk", "phy_clk", "ref_clk";
+- dma-coherent;
+- };
+- };
+-
+- main_r5fss0: r5fss@5c00000 {
+- compatible = "ti,j721s2-r5fss";
+- ti,cluster-mode = <1>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+- <0x5d00000 0x00 0x5d00000 0x20000>;
+- power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
+-
+- main_r5fss0_core0: r5f@5c00000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5c00000 0x00010000>,
+- <0x5c10000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <339>;
+- ti,sci-proc-ids = <0x06 0xff>;
+- resets = <&k3_reset 339 1>;
+- firmware-name = "j784s4-main-r5f0_0-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+-
+- main_r5fss0_core1: r5f@5d00000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5d00000 0x00010000>,
+- <0x5d10000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <340>;
+- ti,sci-proc-ids = <0x07 0xff>;
+- resets = <&k3_reset 340 1>;
+- firmware-name = "j784s4-main-r5f0_1-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+- };
+-
+- main_r5fss1: r5fss@5e00000 {
+- compatible = "ti,j721s2-r5fss";
+- ti,cluster-mode = <1>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+- <0x5f00000 0x00 0x5f00000 0x20000>;
+- power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
+-
+- main_r5fss1_core0: r5f@5e00000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5e00000 0x00010000>,
+- <0x5e10000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <341>;
+- ti,sci-proc-ids = <0x08 0xff>;
+- resets = <&k3_reset 341 1>;
+- firmware-name = "j784s4-main-r5f1_0-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+-
+- main_r5fss1_core1: r5f@5f00000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5f00000 0x00010000>,
+- <0x5f10000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <342>;
+- ti,sci-proc-ids = <0x09 0xff>;
+- resets = <&k3_reset 342 1>;
+- firmware-name = "j784s4-main-r5f1_1-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+- };
+-
+- main_r5fss2: r5fss@5900000 {
+- compatible = "ti,j721s2-r5fss";
+- ti,cluster-mode = <1>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0x5900000 0x00 0x5900000 0x20000>,
+- <0x5a00000 0x00 0x5a00000 0x20000>;
+- power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
+-
+- main_r5fss2_core0: r5f@5900000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5900000 0x00010000>,
+- <0x5910000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <343>;
+- ti,sci-proc-ids = <0x0a 0xff>;
+- resets = <&k3_reset 343 1>;
+- firmware-name = "j784s4-main-r5f2_0-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+-
+- main_r5fss2_core1: r5f@5a00000 {
+- compatible = "ti,j721s2-r5f";
+- reg = <0x5a00000 0x00010000>,
+- <0x5a10000 0x00010000>;
+- reg-names = "atcm", "btcm";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <344>;
+- ti,sci-proc-ids = <0x0b 0xff>;
+- resets = <&k3_reset 344 1>;
+- firmware-name = "j784s4-main-r5f2_1-fw";
+- ti,atcm-enable = <1>;
+- ti,btcm-enable = <1>;
+- ti,loczrama = <1>;
+- };
+- };
+-
+- c71_0: dsp@64800000 {
+- compatible = "ti,j721s2-c71-dsp";
+- reg = <0x00 0x64800000 0x00 0x00080000>,
+- <0x00 0x64e00000 0x00 0x0000c000>;
+- reg-names = "l2sram", "l1dram";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <30>;
+- ti,sci-proc-ids = <0x30 0xff>;
+- resets = <&k3_reset 30 1>;
+- firmware-name = "j784s4-c71_0-fw";
+- status = "disabled";
+- };
+-
+- c71_1: dsp@65800000 {
+- compatible = "ti,j721s2-c71-dsp";
+- reg = <0x00 0x65800000 0x00 0x00080000>,
+- <0x00 0x65e00000 0x00 0x0000c000>;
+- reg-names = "l2sram", "l1dram";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <33>;
+- ti,sci-proc-ids = <0x31 0xff>;
+- resets = <&k3_reset 33 1>;
+- firmware-name = "j784s4-c71_1-fw";
+- status = "disabled";
+- };
+-
+- c71_2: dsp@66800000 {
+- compatible = "ti,j721s2-c71-dsp";
+- reg = <0x00 0x66800000 0x00 0x00080000>,
+- <0x00 0x66e00000 0x00 0x0000c000>;
+- reg-names = "l2sram", "l1dram";
+- ti,sci = <&sms>;
+- ti,sci-dev-id = <37>;
+- ti,sci-proc-ids = <0x32 0xff>;
+- resets = <&k3_reset 37 1>;
+- firmware-name = "j784s4-c71_2-fw";
+- status = "disabled";
+- };
+-
++&cbass_main {
+ c71_3: dsp@67800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x67800000 0x00 0x00080000>,
+ <0x00 0x67e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
++ resets = <&k3_reset 40 1>;
++ firmware-name = "j784s4-c71_3-fw";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <40>;
+ ti,sci-proc-ids = <0x33 0xff>;
+- resets = <&k3_reset 40 1>;
+- firmware-name = "j784s4-c71_3-fw";
+- status = "disabled";
+- };
+-
+- main_esm: esm@700000 {
+- compatible = "ti,j721e-esm";
+- reg = <0x00 0x700000 0x00 0x1000>;
+- ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>,
+- <695>;
+- bootph-pre-ram;
+- };
+-
+- watchdog0: watchdog@2200000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2200000 0x00 0x100>;
+- clocks = <&k3_clks 348 0>;
+- power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 348 0>;
+- assigned-clock-parents = <&k3_clks 348 4>;
+- };
+-
+- watchdog1: watchdog@2210000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2210000 0x00 0x100>;
+- clocks = <&k3_clks 349 0>;
+- power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 349 0>;
+- assigned-clock-parents = <&k3_clks 349 4>;
+- };
+-
+- watchdog2: watchdog@2220000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2220000 0x00 0x100>;
+- clocks = <&k3_clks 350 0>;
+- power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 350 0>;
+- assigned-clock-parents = <&k3_clks 350 4>;
+- };
+-
+- watchdog3: watchdog@2230000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2230000 0x00 0x100>;
+- clocks = <&k3_clks 351 0>;
+- power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 351 0>;
+- assigned-clock-parents = <&k3_clks 351 4>;
+- };
+-
+- watchdog4: watchdog@2240000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2240000 0x00 0x100>;
+- clocks = <&k3_clks 352 0>;
+- power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 352 0>;
+- assigned-clock-parents = <&k3_clks 352 4>;
+- };
+-
+- watchdog5: watchdog@2250000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2250000 0x00 0x100>;
+- clocks = <&k3_clks 353 0>;
+- power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 353 0>;
+- assigned-clock-parents = <&k3_clks 353 4>;
+- };
+-
+- watchdog6: watchdog@2260000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2260000 0x00 0x100>;
+- clocks = <&k3_clks 354 0>;
+- power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 354 0>;
+- assigned-clock-parents = <&k3_clks 354 4>;
+- };
+-
+- watchdog7: watchdog@2270000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2270000 0x00 0x100>;
+- clocks = <&k3_clks 355 0>;
+- power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 355 0>;
+- assigned-clock-parents = <&k3_clks 355 4>;
+- };
+-
+- /*
+- * The following RTI instances are coupled with MCU R5Fs, c7x and
+- * GPU so keeping them reserved as these will be used by their
+- * respective firmware
+- */
+- watchdog8: watchdog@22f0000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x22f0000 0x00 0x100>;
+- clocks = <&k3_clks 360 0>;
+- power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 360 0>;
+- assigned-clock-parents = <&k3_clks 360 4>;
+- /* reserved for GPU */
+- status = "reserved";
+- };
+-
+- watchdog9: watchdog@2300000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2300000 0x00 0x100>;
+- clocks = <&k3_clks 356 0>;
+- power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 356 0>;
+- assigned-clock-parents = <&k3_clks 356 4>;
+- /* reserved for C7X_0 DSP */
+- status = "reserved";
+- };
+-
+- watchdog10: watchdog@2310000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2310000 0x00 0x100>;
+- clocks = <&k3_clks 357 0>;
+- power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 357 0>;
+- assigned-clock-parents = <&k3_clks 357 4>;
+- /* reserved for C7X_1 DSP */
+- status = "reserved";
+- };
+-
+- watchdog11: watchdog@2320000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2320000 0x00 0x100>;
+- clocks = <&k3_clks 358 0>;
+- power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 358 0>;
+- assigned-clock-parents = <&k3_clks 358 4>;
+- /* reserved for C7X_2 DSP */
+- status = "reserved";
+- };
+-
+- watchdog12: watchdog@2330000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2330000 0x00 0x100>;
+- clocks = <&k3_clks 359 0>;
+- power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 359 0>;
+- assigned-clock-parents = <&k3_clks 359 4>;
+- /* reserved for C7X_3 DSP */
+- status = "reserved";
+- };
+-
+- watchdog13: watchdog@23c0000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x23c0000 0x00 0x100>;
+- clocks = <&k3_clks 361 0>;
+- power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 361 0>;
+- assigned-clock-parents = <&k3_clks 361 4>;
+- /* reserved for MAIN_R5F0_0 */
+- status = "reserved";
+- };
+-
+- watchdog14: watchdog@23d0000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x23d0000 0x00 0x100>;
+- clocks = <&k3_clks 362 0>;
+- power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 362 0>;
+- assigned-clock-parents = <&k3_clks 362 4>;
+- /* reserved for MAIN_R5F0_1 */
+- status = "reserved";
+- };
+-
+- watchdog15: watchdog@23e0000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x23e0000 0x00 0x100>;
+- clocks = <&k3_clks 363 0>;
+- power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 363 0>;
+- assigned-clock-parents = <&k3_clks 363 4>;
+- /* reserved for MAIN_R5F1_0 */
+- status = "reserved";
+- };
+-
+- watchdog16: watchdog@23f0000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x23f0000 0x00 0x100>;
+- clocks = <&k3_clks 364 0>;
+- power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 364 0>;
+- assigned-clock-parents = <&k3_clks 364 4>;
+- /* reserved for MAIN_R5F1_1 */
+- status = "reserved";
+- };
+-
+- watchdog17: watchdog@2540000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2540000 0x00 0x100>;
+- clocks = <&k3_clks 365 0>;
+- power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 365 0>;
+- assigned-clock-parents = <&k3_clks 366 4>;
+- /* reserved for MAIN_R5F2_0 */
+- status = "reserved";
+- };
+-
+- watchdog18: watchdog@2550000 {
+- compatible = "ti,j7-rti-wdt";
+- reg = <0x00 0x2550000 0x00 0x100>;
+- clocks = <&k3_clks 366 0>;
+- power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;
+- assigned-clocks = <&k3_clks 366 0>;
+- assigned-clock-parents = <&k3_clks 366 4>;
+- /* reserved for MAIN_R5F2_1 */
+- status = "reserved";
+- };
+-
+- mhdp: bridge@a000000 {
+- compatible = "ti,j721e-mhdp8546";
+- reg = <0x0 0xa000000 0x0 0x30a00>,
+- <0x0 0x4f40000 0x0 0x20>;
+- reg-names = "mhdptx", "j721e-intg";
+- clocks = <&k3_clks 217 11>;
+- interrupt-parent = <&gic500>;
+- interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+- power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
+-
+- dp0_ports: ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- /* Remote-endpoints are on the boards so
+- * ports are defined in the platform dt file.
+- */
+- };
+- };
+-
+- dss: dss@4a00000 {
+- compatible = "ti,j721e-dss";
+- reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+- <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+- <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+- <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+- <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+- <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+- <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+- <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+- <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+- <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+- <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+- <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+- <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+- <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
+- <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
+- <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+- <0x00 0x04af0000 0x00 0x10000>; /* wb */
+- reg-names = "common_m", "common_s0",
+- "common_s1", "common_s2",
+- "vidl1", "vidl2","vid1","vid2",
+- "ovr1", "ovr2", "ovr3", "ovr4",
+- "vp1", "vp2", "vp3", "vp4",
+- "wb";
+- clocks = <&k3_clks 218 0>,
+- <&k3_clks 218 2>,
+- <&k3_clks 218 5>,
+- <&k3_clks 218 14>,
+- <&k3_clks 218 18>;
+- clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+- power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+- interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "common_m",
+- "common_s0",
+- "common_s1",
+- "common_s2";
+ status = "disabled";
+-
+- dss_ports: ports {
+- /* Ports that DSS drives are platform specific
+- * so they are defined in platform dt file.
+- */
+- };
+ };
+
+- mcasp0: mcasp@2b00000 {
+- compatible = "ti,am33xx-mcasp-audio";
+- reg = <0x00 0x02b00000 0x00 0x2000>,
+- <0x00 0x02b08000 0x00 0x1000>;
+- reg-names = "mpu","dat";
+- interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "tx", "rx";
+- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
+- dma-names = "tx", "rx";
+- clocks = <&k3_clks 265 0>;
++ pcie2_rc: pcie@2920000 {
++ compatible = "ti,j784s4-pcie-host";
++ reg = <0x00 0x02920000 0x00 0x1000>,
++ <0x00 0x02927000 0x00 0x400>,
++ <0x00 0x0e000000 0x00 0x00800000>,
++ <0x44 0x00000000 0x00 0x00001000>;
++ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
++ <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
++ interrupt-names = "link_state";
++ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
++ device_type = "pci";
++ max-link-speed = <3>;
++ num-lanes = <2>;
++ power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 334 0>;
+ clock-names = "fck";
+- assigned-clocks = <&k3_clks 265 0>;
+- assigned-clock-parents = <&k3_clks 265 1>;
+- power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xff>;
++ vendor-id = <0x104c>;
++ device-id = <0xb012>;
++ msi-map = <0x0 &gic_its 0x20000 0x10000>;
++ dma-coherent;
++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
++ ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ status = "disabled";
+ };
+
+- mcasp1: mcasp@2b10000 {
+- compatible = "ti,am33xx-mcasp-audio";
+- reg = <0x00 0x02b10000 0x00 0x2000>,
+- <0x00 0x02b18000 0x00 0x1000>;
+- reg-names = "mpu","dat";
+- interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "tx", "rx";
+- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
+- dma-names = "tx", "rx";
+- clocks = <&k3_clks 266 0>;
++ pcie3_rc: pcie@2930000 {
++ compatible = "ti,j784s4-pcie-host";
++ reg = <0x00 0x02930000 0x00 0x1000>,
++ <0x00 0x02937000 0x00 0x400>,
++ <0x00 0x0e800000 0x00 0x00800000>,
++ <0x44 0x10000000 0x00 0x00001000>;
++ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
++ <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
++ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
++ interrupt-names = "link_state";
++ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
++ device_type = "pci";
++ max-link-speed = <3>;
++ num-lanes = <2>;
++ power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 335 0>;
+ clock-names = "fck";
+- assigned-clocks = <&k3_clks 266 0>;
+- assigned-clock-parents = <&k3_clks 266 1>;
+- power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xff>;
++ vendor-id = <0x104c>;
++ device-id = <0xb012>;
++ msi-map = <0x0 &gic_its 0x30000 0x10000>;
++ dma-coherent;
++ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
++ ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ status = "disabled";
+ };
+
+- mcasp2: mcasp@2b20000 {
+- compatible = "ti,am33xx-mcasp-audio";
+- reg = <0x00 0x02b20000 0x00 0x2000>,
+- <0x00 0x02b28000 0x00 0x1000>;
+- reg-names = "mpu","dat";
+- interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "tx", "rx";
+- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
+- dma-names = "tx", "rx";
+- clocks = <&k3_clks 267 0>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 267 0>;
+- assigned-clock-parents = <&k3_clks 267 1>;
+- power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
++ serdes_wiz2: wiz@5020000 {
++ compatible = "ti,j784s4-wiz-10g";
++ ranges = <0x05020000 0x00 0x05020000 0x10000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
++ clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
++ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
++ assigned-clocks = <&k3_clks 406 6>;
++ assigned-clock-parents = <&k3_clks 406 10>;
++ num-lanes = <4>;
++ #reset-cells = <1>;
++ #clock-cells = <1>;
+ status = "disabled";
++
++ serdes2: serdes@5020000 {
++ compatible = "ti,j721e-serdes-10g";
++ reg = <0x05020000 0x010000>;
++ reg-names = "torrent_phy";
++ resets = <&serdes_wiz2 0>;
++ reset-names = "torrent_reset";
++ clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
++ clock-names = "refclk", "phy_en_refclk";
++ assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
++ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
++ <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
++ assigned-clock-parents = <&k3_clks 406 6>,
++ <&k3_clks 406 6>,
++ <&k3_clks 406 6>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <1>;
++ status = "disabled";
++ };
+ };
++};
+
+- mcasp3: mcasp@2b30000 {
+- compatible = "ti,am33xx-mcasp-audio";
+- reg = <0x00 0x02b30000 0x00 0x2000>,
+- <0x00 0x02b38000 0x00 0x1000>;
+- reg-names = "mpu","dat";
+- interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "tx", "rx";
+- dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
+- dma-names = "tx", "rx";
+- clocks = <&k3_clks 268 0>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 268 0>;
+- assigned-clock-parents = <&k3_clks 268 1>;
+- power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
++&scm_conf {
++ pcie2_ctrl: pcie2-ctrl@4078 {
++ compatible = "ti,j784s4-pcie-ctrl", "syscon";
++ reg = <0x4078 0x4>;
+ };
+
+- mcasp4: mcasp@2b40000 {
+- compatible = "ti,am33xx-mcasp-audio";
+- reg = <0x00 0x02b40000 0x00 0x2000>,
+- <0x00 0x02b48000 0x00 0x1000>;
+- reg-names = "mpu","dat";
+- interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "tx", "rx";
+- dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
+- dma-names = "tx", "rx";
+- clocks = <&k3_clks 269 0>;
+- clock-names = "fck";
+- assigned-clocks = <&k3_clks 269 0>;
+- assigned-clock-parents = <&k3_clks 269 1>;
+- power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+- status = "disabled";
++ pcie3_ctrl: pcie3-ctrl@407c {
++ compatible = "ti,j784s4-pcie-ctrl", "syscon";
++ reg = <0x407c 0x4>;
+ };
+ };
+diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+index 5e84c6b4f5ad4..f5afa32157cb8 100644
+--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+@@ -8,18 +8,11 @@
+ *
+ */
+
+-#include <dt-bindings/interrupt-controller/irq.h>
+-#include <dt-bindings/interrupt-controller/arm-gic.h>
+-#include <dt-bindings/soc/ti,sci_pm_domain.h>
+-
+-#include "k3-pinctrl.h"
++#include "k3-j784s4-j742s2-common.dtsi"
+
+ / {
+ model = "Texas Instruments K3 J784S4 SoC";
+ compatible = "ti,j784s4";
+- interrupt-parent = <&gic500>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+@@ -174,130 +167,6 @@ cpu7: cpu@103 {
+ next-level-cache = <&L2_1>;
+ };
+ };
+-
+- L2_0: l2-cache0 {
+- compatible = "cache";
+- cache-level = <2>;
+- cache-unified;
+- cache-size = <0x200000>;
+- cache-line-size = <64>;
+- cache-sets = <1024>;
+- next-level-cache = <&msmc_l3>;
+- };
+-
+- L2_1: l2-cache1 {
+- compatible = "cache";
+- cache-level = <2>;
+- cache-unified;
+- cache-size = <0x200000>;
+- cache-line-size = <64>;
+- cache-sets = <1024>;
+- next-level-cache = <&msmc_l3>;
+- };
+-
+- msmc_l3: l3-cache0 {
+- compatible = "cache";
+- cache-level = <3>;
+- cache-unified;
+- };
+-
+- firmware {
+- optee {
+- compatible = "linaro,optee-tz";
+- method = "smc";
+- };
+-
+- psci: psci {
+- compatible = "arm,psci-1.0";
+- method = "smc";
+- };
+- };
+-
+- a72_timer0: timer-cl0-cpu0 {
+- compatible = "arm,armv8-timer";
+- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+- };
+-
+- pmu: pmu {
+- compatible = "arm,cortex-a72-pmu";
+- /* Recommendation from GIC500 TRM Table A.3 */
+- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- cbass_main: bus@100000 {
+- bootph-all;
+- compatible = "simple-bus";
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+- <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+- <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
+- <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+- <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
+- <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
+- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
+- <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
+- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
+- <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
+- <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
+- <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
+- <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
+- <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+- <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
+- <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
+- <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
+- <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
+- <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+- <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
+- <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+- <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
+- <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
+- <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
+- <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
+- <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+-
+- /* MCUSS_WKUP Range */
+- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+- <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+-
+- cbass_mcu_wakeup: bus@28380000 {
+- bootph-all;
+- compatible = "simple-bus";
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+- <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+- <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
+- <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
+- };
+- };
+-
+- thermal_zones: thermal-zones {
+- #include "k3-j784s4-thermal.dtsi"
+- };
+ };
+
+-/* Now include peripherals from each bus segment */
+ #include "k3-j784s4-main.dtsi"
+-#include "k3-j784s4-mcu-wakeup.dtsi"
+--
+2.39.5
+
--- /dev/null
+From 1619c28eaea9a82e38ec4b80b06d4c946b6c7809 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 10 Mar 2025 19:54:53 +0800
+Subject: block: make sure ->nr_integrity_segments is cloned in
+ blk_rq_prep_clone
+
+From: Ming Lei <ming.lei@redhat.com>
+
+[ Upstream commit fc0e982b8a3a169b1c654d9a1aa45bf292943ef2 ]
+
+Make sure ->nr_integrity_segments is cloned in blk_rq_prep_clone(),
+otherwise requests cloned by device-mapper multipath will not have the
+proper nr_integrity_segments values set, then BUG() is hit from
+sg_alloc_table_chained().
+
+Fixes: b0fd271d5fba ("block: add request clone interface (v2)")
+Cc: stable@vger.kernel.org
+Cc: Christoph Hellwig <hch@infradead.org>
+Signed-off-by: Ming Lei <ming.lei@redhat.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Link: https://lore.kernel.org/r/20250310115453.2271109-1-ming.lei@redhat.com
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ block/blk-mq.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/block/blk-mq.c b/block/blk-mq.c
+index 5e6afda59e7a1..a7765e96cf40e 100644
+--- a/block/blk-mq.c
++++ b/block/blk-mq.c
+@@ -3306,6 +3306,7 @@ int blk_rq_prep_clone(struct request *rq, struct request *rq_src,
+ rq->special_vec = rq_src->special_vec;
+ }
+ rq->nr_phys_segments = rq_src->nr_phys_segments;
++ rq->nr_integrity_segments = rq_src->nr_integrity_segments;
+
+ if (rq->bio && blk_crypto_rq_bio_prep(rq, rq->bio, gfp_mask) < 0)
+ goto free_and_out;
+--
+2.39.5
+
--- /dev/null
+From 27513f0cf8d4e962586f0163629d54e27b77f874 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Nov 2024 18:00:39 +0100
+Subject: block: remove the ioprio field from struct request
+
+From: Christoph Hellwig <hch@lst.de>
+
+[ Upstream commit 6975c1a486a40446b5bc77a89d9c520f8296fd08 ]
+
+The request ioprio is only initialized from the first attached bio,
+so requests without a bio already never set it. Directly use the
+bio field instead.
+
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Link: https://lore.kernel.org/r/20241112170050.1612998-3-hch@lst.de
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Stable-dep-of: fc0e982b8a3a ("block: make sure ->nr_integrity_segments is cloned in blk_rq_prep_clone")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ block/blk-merge.c | 10 ++++------
+ block/blk-mq.c | 3 +--
+ include/linux/blk-mq.h | 7 +++----
+ include/trace/events/block.h | 6 +++---
+ 4 files changed, 11 insertions(+), 15 deletions(-)
+
+diff --git a/block/blk-merge.c b/block/blk-merge.c
+index bc909bd894fae..f575cc1705b3f 100644
+--- a/block/blk-merge.c
++++ b/block/blk-merge.c
+@@ -868,11 +868,10 @@ static struct request *attempt_merge(struct request_queue *q,
+ /* Don't merge requests with different write hints. */
+ if (req->bio->bi_write_hint != next->bio->bi_write_hint)
+ return NULL;
++ if (req->bio->bi_ioprio != next->bio->bi_ioprio)
++ return NULL;
+ }
+
+- if (req->ioprio != next->ioprio)
+- return NULL;
+-
+ if (!blk_atomic_write_mergeable_rqs(req, next))
+ return NULL;
+
+@@ -1004,11 +1003,10 @@ bool blk_rq_merge_ok(struct request *rq, struct bio *bio)
+ /* Don't merge requests with different write hints. */
+ if (rq->bio->bi_write_hint != bio->bi_write_hint)
+ return false;
++ if (rq->bio->bi_ioprio != bio->bi_ioprio)
++ return false;
+ }
+
+- if (rq->ioprio != bio_prio(bio))
+- return false;
+-
+ if (blk_atomic_write_mergeable_rq_bio(rq, bio) == false)
+ return false;
+
+diff --git a/block/blk-mq.c b/block/blk-mq.c
+index e3a0f521335bb..5e6afda59e7a1 100644
+--- a/block/blk-mq.c
++++ b/block/blk-mq.c
+@@ -870,7 +870,7 @@ static void blk_print_req_error(struct request *req, blk_status_t status)
+ blk_op_str(req_op(req)),
+ (__force u32)(req->cmd_flags & ~REQ_OP_MASK),
+ req->nr_phys_segments,
+- IOPRIO_PRIO_CLASS(req->ioprio));
++ IOPRIO_PRIO_CLASS(req_get_ioprio(req)));
+ }
+
+ /*
+@@ -3306,7 +3306,6 @@ int blk_rq_prep_clone(struct request *rq, struct request *rq_src,
+ rq->special_vec = rq_src->special_vec;
+ }
+ rq->nr_phys_segments = rq_src->nr_phys_segments;
+- rq->ioprio = rq_src->ioprio;
+
+ if (rq->bio && blk_crypto_rq_bio_prep(rq, rq->bio, gfp_mask) < 0)
+ goto free_and_out;
+diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h
+index 07c3934080bad..959f8f82a6509 100644
+--- a/include/linux/blk-mq.h
++++ b/include/linux/blk-mq.h
+@@ -156,8 +156,6 @@ struct request {
+ struct blk_crypto_keyslot *crypt_keyslot;
+ #endif
+
+- unsigned short ioprio;
+-
+ enum mq_rq_state state;
+ atomic_t ref;
+
+@@ -221,7 +219,9 @@ static inline bool blk_rq_is_passthrough(struct request *rq)
+
+ static inline unsigned short req_get_ioprio(struct request *req)
+ {
+- return req->ioprio;
++ if (req->bio)
++ return req->bio->bi_ioprio;
++ return 0;
+ }
+
+ #define rq_data_dir(rq) (op_is_write(req_op(rq)) ? WRITE : READ)
+@@ -1009,7 +1009,6 @@ static inline void blk_rq_bio_prep(struct request *rq, struct bio *bio,
+ rq->nr_phys_segments = nr_segs;
+ rq->__data_len = bio->bi_iter.bi_size;
+ rq->bio = rq->biotail = bio;
+- rq->ioprio = bio_prio(bio);
+ }
+
+ void blk_mq_hctx_set_fq_lock_class(struct blk_mq_hw_ctx *hctx,
+diff --git a/include/trace/events/block.h b/include/trace/events/block.h
+index 1527d5d45e01a..bd0ea07338eb6 100644
+--- a/include/trace/events/block.h
++++ b/include/trace/events/block.h
+@@ -99,7 +99,7 @@ TRACE_EVENT(block_rq_requeue,
+ __entry->dev = rq->q->disk ? disk_devt(rq->q->disk) : 0;
+ __entry->sector = blk_rq_trace_sector(rq);
+ __entry->nr_sector = blk_rq_trace_nr_sectors(rq);
+- __entry->ioprio = rq->ioprio;
++ __entry->ioprio = req_get_ioprio(rq);
+
+ blk_fill_rwbs(__entry->rwbs, rq->cmd_flags);
+ __get_str(cmd)[0] = '\0';
+@@ -136,7 +136,7 @@ DECLARE_EVENT_CLASS(block_rq_completion,
+ __entry->sector = blk_rq_pos(rq);
+ __entry->nr_sector = nr_bytes >> 9;
+ __entry->error = blk_status_to_errno(error);
+- __entry->ioprio = rq->ioprio;
++ __entry->ioprio = req_get_ioprio(rq);
+
+ blk_fill_rwbs(__entry->rwbs, rq->cmd_flags);
+ __get_str(cmd)[0] = '\0';
+@@ -209,7 +209,7 @@ DECLARE_EVENT_CLASS(block_rq,
+ __entry->sector = blk_rq_trace_sector(rq);
+ __entry->nr_sector = blk_rq_trace_nr_sectors(rq);
+ __entry->bytes = blk_rq_bytes(rq);
+- __entry->ioprio = rq->ioprio;
++ __entry->ioprio = req_get_ioprio(rq);
+
+ blk_fill_rwbs(__entry->rwbs, rq->cmd_flags);
+ __get_str(cmd)[0] = '\0';
+--
+2.39.5
+
--- /dev/null
+From 41dcfec6cecca336b5b71ccb4816de5697ea600a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Nov 2024 18:00:38 +0100
+Subject: block: remove the write_hint field from struct request
+
+From: Christoph Hellwig <hch@lst.de>
+
+[ Upstream commit 61952bb73486fff0f5550bccdf4062d9dd0fb163 ]
+
+The write_hint is only used for read/write requests, which must have a
+bio attached to them. Just use the bio field instead.
+
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Link: https://lore.kernel.org/r/20241112170050.1612998-2-hch@lst.de
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Stable-dep-of: fc0e982b8a3a ("block: make sure ->nr_integrity_segments is cloned in blk_rq_prep_clone")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ block/blk-merge.c | 16 ++++++++++------
+ block/blk-mq.c | 2 --
+ drivers/scsi/sd.c | 6 +++---
+ include/linux/blk-mq.h | 1 -
+ 4 files changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/block/blk-merge.c b/block/blk-merge.c
+index ceac64e796ea8..bc909bd894fae 100644
+--- a/block/blk-merge.c
++++ b/block/blk-merge.c
+@@ -864,9 +864,11 @@ static struct request *attempt_merge(struct request_queue *q,
+ if (rq_data_dir(req) != rq_data_dir(next))
+ return NULL;
+
+- /* Don't merge requests with different write hints. */
+- if (req->write_hint != next->write_hint)
+- return NULL;
++ if (req->bio && next->bio) {
++ /* Don't merge requests with different write hints. */
++ if (req->bio->bi_write_hint != next->bio->bi_write_hint)
++ return NULL;
++ }
+
+ if (req->ioprio != next->ioprio)
+ return NULL;
+@@ -998,9 +1000,11 @@ bool blk_rq_merge_ok(struct request *rq, struct bio *bio)
+ if (!bio_crypt_rq_ctx_compatible(rq, bio))
+ return false;
+
+- /* Don't merge requests with different write hints. */
+- if (rq->write_hint != bio->bi_write_hint)
+- return false;
++ if (rq->bio) {
++ /* Don't merge requests with different write hints. */
++ if (rq->bio->bi_write_hint != bio->bi_write_hint)
++ return false;
++ }
+
+ if (rq->ioprio != bio_prio(bio))
+ return false;
+diff --git a/block/blk-mq.c b/block/blk-mq.c
+index f26bee5626936..e3a0f521335bb 100644
+--- a/block/blk-mq.c
++++ b/block/blk-mq.c
+@@ -2654,7 +2654,6 @@ static void blk_mq_bio_to_request(struct request *rq, struct bio *bio,
+ rq->cmd_flags |= REQ_FAILFAST_MASK;
+
+ rq->__sector = bio->bi_iter.bi_sector;
+- rq->write_hint = bio->bi_write_hint;
+ blk_rq_bio_prep(rq, bio, nr_segs);
+ if (bio_integrity(bio))
+ rq->nr_integrity_segments = blk_rq_count_integrity_sg(rq->q,
+@@ -3308,7 +3307,6 @@ int blk_rq_prep_clone(struct request *rq, struct request *rq_src,
+ }
+ rq->nr_phys_segments = rq_src->nr_phys_segments;
+ rq->ioprio = rq_src->ioprio;
+- rq->write_hint = rq_src->write_hint;
+
+ if (rq->bio && blk_crypto_rq_bio_prep(rq, rq->bio, gfp_mask) < 0)
+ goto free_and_out;
+diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
+index ca4bc0ac76adc..8947dab132d78 100644
+--- a/drivers/scsi/sd.c
++++ b/drivers/scsi/sd.c
+@@ -1190,8 +1190,8 @@ static u8 sd_group_number(struct scsi_cmnd *cmd)
+ if (!sdkp->rscs)
+ return 0;
+
+- return min3((u32)rq->write_hint, (u32)sdkp->permanent_stream_count,
+- 0x3fu);
++ return min3((u32)rq->bio->bi_write_hint,
++ (u32)sdkp->permanent_stream_count, 0x3fu);
+ }
+
+ static blk_status_t sd_setup_rw32_cmnd(struct scsi_cmnd *cmd, bool write,
+@@ -1389,7 +1389,7 @@ static blk_status_t sd_setup_read_write_cmnd(struct scsi_cmnd *cmd)
+ ret = sd_setup_rw16_cmnd(cmd, write, lba, nr_blocks,
+ protect | fua, dld);
+ } else if ((nr_blocks > 0xff) || (lba > 0x1fffff) ||
+- sdp->use_10_for_rw || protect || rq->write_hint) {
++ sdp->use_10_for_rw || protect || rq->bio->bi_write_hint) {
+ ret = sd_setup_rw10_cmnd(cmd, write, lba, nr_blocks,
+ protect | fua);
+ } else {
+diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h
+index 318245b4e38fb..07c3934080bad 100644
+--- a/include/linux/blk-mq.h
++++ b/include/linux/blk-mq.h
+@@ -156,7 +156,6 @@ struct request {
+ struct blk_crypto_keyslot *crypt_keyslot;
+ #endif
+
+- enum rw_hint write_hint;
+ unsigned short ioprio;
+
+ enum mq_rq_state state;
+--
+2.39.5
+
--- /dev/null
+From bef04d532ce0878291593d97374ee0598def9629 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 8 Apr 2025 21:27:15 -0400
+Subject: drm/amd/display/dml2: use vzalloc rather than kzalloc
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit cd9e6d6fdd2de60bfb4672387c17d4ee7157cf8e ]
+
+The structures are large and they do not require contiguous
+memory so use vzalloc.
+
+Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4126
+Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 20c50a9a793300a1fc82f3ddd0e3c68f8213fbef)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 11 ++++++-----
+ drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 6 ++++--
+ 2 files changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+index dedf0fd3eb276..e3e4f40bd4123 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+@@ -2,6 +2,7 @@
+ //
+ // Copyright 2024 Advanced Micro Devices, Inc.
+
++#include <linux/vmalloc.h>
+
+ #include "dml2_internal_types.h"
+ #include "dml_top.h"
+@@ -13,11 +14,11 @@
+
+ static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
+ {
+- *dml_ctx = kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
++ *dml_ctx = vzalloc(sizeof(struct dml2_context));
+ if (!(*dml_ctx))
+ return false;
+
+- (*dml_ctx)->v21.dml_init.dml2_instance = kzalloc(sizeof(struct dml2_instance), GFP_KERNEL);
++ (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance));
+ if (!((*dml_ctx)->v21.dml_init.dml2_instance))
+ return false;
+
+@@ -27,7 +28,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
+ (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config;
+ (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config;
+
+- (*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL);
++ (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming));
+ if (!((*dml_ctx)->v21.mode_programming.programming))
+ return false;
+
+@@ -116,8 +117,8 @@ bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const s
+
+ void dml21_destroy(struct dml2_context *dml2)
+ {
+- kfree(dml2->v21.dml_init.dml2_instance);
+- kfree(dml2->v21.mode_programming.programming);
++ vfree(dml2->v21.dml_init.dml2_instance);
++ vfree(dml2->v21.mode_programming.programming);
+ }
+
+ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,
+diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+index cb2cb89dfecb2..03812f862b3d6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+@@ -24,6 +24,8 @@
+ *
+ */
+
++#include <linux/vmalloc.h>
++
+ #include "display_mode_core.h"
+ #include "dml2_internal_types.h"
+ #include "dml2_utils.h"
+@@ -749,7 +751,7 @@ bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2
+
+ static inline struct dml2_context *dml2_allocate_memory(void)
+ {
+- return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
++ return (struct dml2_context *) vzalloc(sizeof(struct dml2_context));
+ }
+
+ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
+@@ -820,7 +822,7 @@ void dml2_destroy(struct dml2_context *dml2)
+
+ if (dml2->architecture == dml2_architecture_21)
+ dml21_destroy(dml2);
+- kfree(dml2);
++ vfree(dml2);
+ }
+
+ void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,
+--
+2.39.5
+
--- /dev/null
+From 2288fb0fc5f673aeebe7f8f35f05f9b89900b192 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 17 Sep 2024 22:01:19 +0530
+Subject: drm/amd/display: Fix unnecessary cast warnings from checkpatch
+
+From: Rohit Chavan <roheetchavan@gmail.com>
+
+[ Upstream commit c299cb6eafaf76d0cb4094623d6401c45d8bd0dc ]
+
+This patch addresses warnings produced by the checkpatch script
+related to unnecessary casts that could potentially hide bugs.
+
+The specific warnings are as follows:
+- Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:16
+- Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:20
+- Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:30
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rohit Chavan <roheetchavan@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: cd9e6d6fdd2d ("drm/amd/display/dml2: use vzalloc rather than kzalloc")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+index cb187604744e9..dedf0fd3eb276 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+@@ -13,11 +13,11 @@
+
+ static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
+ {
+- *dml_ctx = (struct dml2_context *)kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
++ *dml_ctx = kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
+ if (!(*dml_ctx))
+ return false;
+
+- (*dml_ctx)->v21.dml_init.dml2_instance = (struct dml2_instance *)kzalloc(sizeof(struct dml2_instance), GFP_KERNEL);
++ (*dml_ctx)->v21.dml_init.dml2_instance = kzalloc(sizeof(struct dml2_instance), GFP_KERNEL);
+ if (!((*dml_ctx)->v21.dml_init.dml2_instance))
+ return false;
+
+@@ -27,7 +27,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
+ (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config;
+ (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config;
+
+- (*dml_ctx)->v21.mode_programming.programming = (struct dml2_display_cfg_programming *)kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL);
++ (*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL);
+ if (!((*dml_ctx)->v21.mode_programming.programming))
+ return false;
+
+--
+2.39.5
+
--- /dev/null
+From 7e65f1788e9e79d1042746004a0e9bfa5dd8c977 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 25 Mar 2025 15:47:10 -0700
+Subject: drm/xe/bmg: Add one additional PCI ID
+
+From: Matt Roper <matthew.d.roper@intel.com>
+
+[ Upstream commit 5529df92b8e8cbb4b14a226665888f74648260ad ]
+
+One additional BMG PCI ID has been added to the spec; make sure our
+driver recognizes devices with this ID properly.
+
+Bspec: 68090
+Cc: stable@vger.kernel.org # v6.12+
+Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Link: https://lore.kernel.org/r/20250325224709.4073080-2-matthew.d.roper@intel.com
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+(cherry picked from commit cca9734ebe55f6af11ce8d57ca1afdc4d158c808)
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/drm/intel/i915_pciids.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h
+index dacea289acaf5..1ff00e3d4418e 100644
+--- a/include/drm/intel/i915_pciids.h
++++ b/include/drm/intel/i915_pciids.h
+@@ -810,6 +810,7 @@
+ MACRO__(0xE20C, ## __VA_ARGS__), \
+ MACRO__(0xE20D, ## __VA_ARGS__), \
+ MACRO__(0xE210, ## __VA_ARGS__), \
++ MACRO__(0xE211, ## __VA_ARGS__), \
+ MACRO__(0xE212, ## __VA_ARGS__), \
+ MACRO__(0xE215, ## __VA_ARGS__), \
+ MACRO__(0xE216, ## __VA_ARGS__)
+--
+2.39.5
+
--- /dev/null
+From 42ca90a4f0bcc4d4a71f8618c78460bf1f0fd661 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Mar 2025 18:00:29 -0300
+Subject: iio: adc: ad7768-1: Fix conversion result sign
+
+From: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
+
+[ Upstream commit 8236644f5ecb180e80ad92d691c22bc509b747bb ]
+
+The ad7768-1 ADC output code is two's complement, meaning that the voltage
+conversion result is a signed value.. Since the value is a 24 bit one,
+stored in a 32 bit variable, the sign should be extended in order to get
+the correct representation.
+
+Also the channel description has been updated to signed representation,
+to match the ADC specifications.
+
+Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support")
+Reviewed-by: David Lechner <dlechner@baylibre.com>
+Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
+Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
+Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
+Cc: <Stable@vger.kernel.org>
+Link: https://patch.msgid.link/505994d3b71c2aa38ba714d909a68e021f12124c.1741268122.git.Jonathan.Santos@analog.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/ad7768-1.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
+index c78243a68b6e0..157a0df97f971 100644
+--- a/drivers/iio/adc/ad7768-1.c
++++ b/drivers/iio/adc/ad7768-1.c
+@@ -142,7 +142,7 @@ static const struct iio_chan_spec ad7768_channels[] = {
+ .channel = 0,
+ .scan_index = 0,
+ .scan_type = {
+- .sign = 'u',
++ .sign = 's',
+ .realbits = 24,
+ .storagebits = 32,
+ .shift = 8,
+@@ -374,7 +374,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev,
+ iio_device_release_direct_mode(indio_dev);
+ if (ret < 0)
+ return ret;
+- *val = ret;
++ *val = sign_extend32(ret, chan->scan_type.realbits - 1);
+
+ return IIO_VAL_INT;
+
+--
+2.39.5
+
--- /dev/null
+From 50c047059aeb207983a448f412dcc5f072926ee2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Feb 2025 14:16:12 +0000
+Subject: iio: adc: ad7768-1: Move setting of val a bit later to avoid
+ unnecessary return value check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+
+[ Upstream commit 0af1c801a15225304a6328258efbf2bee245c654 ]
+
+The data used is all in local variables so there is no advantage
+in setting *val = ret with the direct mode claim held.
+Move it later to after error check.
+
+Reviewed-by: Nuno Sá <nuno.sa@analog.com>
+Link: https://patch.msgid.link/20250217141630.897334-13-jic23@kernel.org
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Stable-dep-of: 8236644f5ecb ("iio: adc: ad7768-1: Fix conversion result sign")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/iio/adc/ad7768-1.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
+index 6f8816483f1a0..c78243a68b6e0 100644
+--- a/drivers/iio/adc/ad7768-1.c
++++ b/drivers/iio/adc/ad7768-1.c
+@@ -370,12 +370,11 @@ static int ad7768_read_raw(struct iio_dev *indio_dev,
+ return ret;
+
+ ret = ad7768_scan_direct(indio_dev);
+- if (ret >= 0)
+- *val = ret;
+
+ iio_device_release_direct_mode(indio_dev);
+ if (ret < 0)
+ return ret;
++ *val = ret;
+
+ return IIO_VAL_INT;
+
+--
+2.39.5
+
--- /dev/null
+From d2e719afcfcd9f2b7111b0bd6fdd397afa4fb345 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 22 Nov 2024 16:14:37 +0900
+Subject: ksmbd: add netdev-up/down event debug print
+
+From: Namjae Jeon <linkinjeon@kernel.org>
+
+[ Upstream commit 5f3f274e2ce68999b49901de4794c4b04125b154 ]
+
+Add netdev-up/down event debug print to find what netdev is connected or
+disconnected.
+
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Stable-dep-of: 21a4e47578d4 ("ksmbd: fix use-after-free in __smb2_lease_break_noti()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/smb/server/transport_tcp.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/fs/smb/server/transport_tcp.c b/fs/smb/server/transport_tcp.c
+index cc77ad4f765a9..0d9007285e30b 100644
+--- a/fs/smb/server/transport_tcp.c
++++ b/fs/smb/server/transport_tcp.c
+@@ -521,6 +521,8 @@ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ found = 1;
+ if (iface->state != IFACE_STATE_DOWN)
+ break;
++ ksmbd_debug(CONN, "netdev-up event: netdev(%s) is going up\n",
++ iface->name);
+ ret = create_socket(iface);
+ if (ret)
+ return NOTIFY_OK;
+@@ -531,6 +533,8 @@ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ iface = alloc_iface(kstrdup(netdev->name, KSMBD_DEFAULT_GFP));
+ if (!iface)
+ return NOTIFY_OK;
++ ksmbd_debug(CONN, "netdev-up event: netdev(%s) is going up\n",
++ iface->name);
+ ret = create_socket(iface);
+ if (ret)
+ break;
+@@ -540,6 +544,8 @@ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ list_for_each_entry(iface, &iface_list, entry) {
+ if (!strcmp(iface->name, netdev->name) &&
+ iface->state == IFACE_STATE_CONFIGURED) {
++ ksmbd_debug(CONN, "netdev-down event: netdev(%s) is going down\n",
++ iface->name);
+ tcp_stop_kthread(iface->ksmbd_kthread);
+ iface->ksmbd_kthread = NULL;
+ mutex_lock(&iface->sock_release_lock);
+--
+2.39.5
+
--- /dev/null
+From 5eec086e807f243afac4a183250c31e720858645 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 10 Jan 2025 13:37:05 +0900
+Subject: ksmbd: browse interfaces list on FSCTL_QUERY_INTERFACE_INFO IOCTL
+
+From: Namjae Jeon <linkinjeon@kernel.org>
+
+[ Upstream commit b2d99376c5d61eb60ffdb6c503e4b6c8f9712ddd ]
+
+ksmbd.mount will give each interfaces list and bind_interfaces_only flags
+to ksmbd server. Previously, the interfaces list was sent only
+when bind_interfaces_only was enabled.
+ksmbd server browse only interfaces list given from ksmbd.conf on
+FSCTL_QUERY_INTERFACE_INFO IOCTL.
+
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Stable-dep-of: 21a4e47578d4 ("ksmbd: fix use-after-free in __smb2_lease_break_noti()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/smb/server/ksmbd_netlink.h | 3 +-
+ fs/smb/server/server.h | 1 +
+ fs/smb/server/smb2pdu.c | 4 ++
+ fs/smb/server/transport_ipc.c | 1 +
+ fs/smb/server/transport_tcp.c | 73 +++++++++++++++--------------------
+ fs/smb/server/transport_tcp.h | 1 +
+ 6 files changed, 41 insertions(+), 42 deletions(-)
+
+diff --git a/fs/smb/server/ksmbd_netlink.h b/fs/smb/server/ksmbd_netlink.h
+index 3d01d9d152934..3f07a612c05b4 100644
+--- a/fs/smb/server/ksmbd_netlink.h
++++ b/fs/smb/server/ksmbd_netlink.h
+@@ -111,7 +111,8 @@ struct ksmbd_startup_request {
+ __u32 smb2_max_credits; /* MAX credits */
+ __u32 smbd_max_io_size; /* smbd read write size */
+ __u32 max_connections; /* Number of maximum simultaneous connections */
+- __u32 reserved[126]; /* Reserved room */
++ __s8 bind_interfaces_only;
++ __s8 reserved[503]; /* Reserved room */
+ __u32 ifc_list_sz; /* interfaces list size */
+ __s8 ____payload[];
+ };
+diff --git a/fs/smb/server/server.h b/fs/smb/server/server.h
+index 94187628ff089..995555febe7d1 100644
+--- a/fs/smb/server/server.h
++++ b/fs/smb/server/server.h
+@@ -46,6 +46,7 @@ struct ksmbd_server_config {
+
+ char *conf[SERVER_CONF_WORK_GROUP + 1];
+ struct task_struct *dh_task;
++ bool bind_interfaces_only;
+ };
+
+ extern struct ksmbd_server_config server_conf;
+diff --git a/fs/smb/server/smb2pdu.c b/fs/smb/server/smb2pdu.c
+index dfae37951312f..6b9286c963439 100644
+--- a/fs/smb/server/smb2pdu.c
++++ b/fs/smb/server/smb2pdu.c
+@@ -38,6 +38,7 @@
+ #include "mgmt/user_session.h"
+ #include "mgmt/ksmbd_ida.h"
+ #include "ndr.h"
++#include "transport_tcp.h"
+
+ static void __wbuf(struct ksmbd_work *work, void **req, void **rsp)
+ {
+@@ -7771,6 +7772,9 @@ static int fsctl_query_iface_info_ioctl(struct ksmbd_conn *conn,
+ if (netdev->type == ARPHRD_LOOPBACK)
+ continue;
+
++ if (!ksmbd_find_netdev_name_iface_list(netdev->name))
++ continue;
++
+ flags = dev_get_flags(netdev);
+ if (!(flags & IFF_RUNNING))
+ continue;
+diff --git a/fs/smb/server/transport_ipc.c b/fs/smb/server/transport_ipc.c
+index 2e17164efc91a..2da2a5f6b983a 100644
+--- a/fs/smb/server/transport_ipc.c
++++ b/fs/smb/server/transport_ipc.c
+@@ -338,6 +338,7 @@ static int ipc_server_config_on_startup(struct ksmbd_startup_request *req)
+ ret = ksmbd_set_netbios_name(req->netbios_name);
+ ret |= ksmbd_set_server_string(req->server_string);
+ ret |= ksmbd_set_work_group(req->work_group);
++ server_conf.bind_interfaces_only = req->bind_interfaces_only;
+ ret |= ksmbd_tcp_set_interfaces(KSMBD_STARTUP_CONFIG_INTERFACES(req),
+ req->ifc_list_sz);
+ out:
+diff --git a/fs/smb/server/transport_tcp.c b/fs/smb/server/transport_tcp.c
+index 0d9007285e30b..7f38a3c3f5bd6 100644
+--- a/fs/smb/server/transport_tcp.c
++++ b/fs/smb/server/transport_tcp.c
+@@ -504,32 +504,37 @@ static int create_socket(struct interface *iface)
+ return ret;
+ }
+
++struct interface *ksmbd_find_netdev_name_iface_list(char *netdev_name)
++{
++ struct interface *iface;
++
++ list_for_each_entry(iface, &iface_list, entry)
++ if (!strcmp(iface->name, netdev_name))
++ return iface;
++ return NULL;
++}
++
+ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ void *ptr)
+ {
+ struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
+ struct interface *iface;
+- int ret, found = 0;
++ int ret;
+
+ switch (event) {
+ case NETDEV_UP:
+ if (netif_is_bridge_port(netdev))
+ return NOTIFY_OK;
+
+- list_for_each_entry(iface, &iface_list, entry) {
+- if (!strcmp(iface->name, netdev->name)) {
+- found = 1;
+- if (iface->state != IFACE_STATE_DOWN)
+- break;
+- ksmbd_debug(CONN, "netdev-up event: netdev(%s) is going up\n",
+- iface->name);
+- ret = create_socket(iface);
+- if (ret)
+- return NOTIFY_OK;
+- break;
+- }
++ iface = ksmbd_find_netdev_name_iface_list(netdev->name);
++ if (iface && iface->state == IFACE_STATE_DOWN) {
++ ksmbd_debug(CONN, "netdev-up event: netdev(%s) is going up\n",
++ iface->name);
++ ret = create_socket(iface);
++ if (ret)
++ return NOTIFY_OK;
+ }
+- if (!found && bind_additional_ifaces) {
++ if (!iface && bind_additional_ifaces) {
+ iface = alloc_iface(kstrdup(netdev->name, KSMBD_DEFAULT_GFP));
+ if (!iface)
+ return NOTIFY_OK;
+@@ -541,21 +546,19 @@ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ }
+ break;
+ case NETDEV_DOWN:
+- list_for_each_entry(iface, &iface_list, entry) {
+- if (!strcmp(iface->name, netdev->name) &&
+- iface->state == IFACE_STATE_CONFIGURED) {
+- ksmbd_debug(CONN, "netdev-down event: netdev(%s) is going down\n",
+- iface->name);
+- tcp_stop_kthread(iface->ksmbd_kthread);
+- iface->ksmbd_kthread = NULL;
+- mutex_lock(&iface->sock_release_lock);
+- tcp_destroy_socket(iface->ksmbd_socket);
+- iface->ksmbd_socket = NULL;
+- mutex_unlock(&iface->sock_release_lock);
+-
+- iface->state = IFACE_STATE_DOWN;
+- break;
+- }
++ iface = ksmbd_find_netdev_name_iface_list(netdev->name);
++ if (iface && iface->state == IFACE_STATE_CONFIGURED) {
++ ksmbd_debug(CONN, "netdev-down event: netdev(%s) is going down\n",
++ iface->name);
++ tcp_stop_kthread(iface->ksmbd_kthread);
++ iface->ksmbd_kthread = NULL;
++ mutex_lock(&iface->sock_release_lock);
++ tcp_destroy_socket(iface->ksmbd_socket);
++ iface->ksmbd_socket = NULL;
++ mutex_unlock(&iface->sock_release_lock);
++
++ iface->state = IFACE_STATE_DOWN;
++ break;
+ }
+ break;
+ }
+@@ -624,18 +627,6 @@ int ksmbd_tcp_set_interfaces(char *ifc_list, int ifc_list_sz)
+ int sz = 0;
+
+ if (!ifc_list_sz) {
+- struct net_device *netdev;
+-
+- rtnl_lock();
+- for_each_netdev(&init_net, netdev) {
+- if (netif_is_bridge_port(netdev))
+- continue;
+- if (!alloc_iface(kstrdup(netdev->name, KSMBD_DEFAULT_GFP))) {
+- rtnl_unlock();
+- return -ENOMEM;
+- }
+- }
+- rtnl_unlock();
+ bind_additional_ifaces = 1;
+ return 0;
+ }
+diff --git a/fs/smb/server/transport_tcp.h b/fs/smb/server/transport_tcp.h
+index e338bebe322f1..8c9aa624cfe3c 100644
+--- a/fs/smb/server/transport_tcp.h
++++ b/fs/smb/server/transport_tcp.h
+@@ -7,6 +7,7 @@
+ #define __KSMBD_TRANSPORT_TCP_H__
+
+ int ksmbd_tcp_set_interfaces(char *ifc_list, int ifc_list_sz);
++struct interface *ksmbd_find_netdev_name_iface_list(char *netdev_name);
+ int ksmbd_tcp_init(void);
+ void ksmbd_tcp_destroy(void);
+
+--
+2.39.5
+
--- /dev/null
+From c31c350627cae6c0415d2c8a31d0e75060677b33 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 11 Apr 2025 15:19:46 +0900
+Subject: ksmbd: fix use-after-free in __smb2_lease_break_noti()
+
+From: Namjae Jeon <linkinjeon@kernel.org>
+
+[ Upstream commit 21a4e47578d44c6b37c4fc4aba8ed7cc8dbb13de ]
+
+Move tcp_transport free to ksmbd_conn_free. If ksmbd connection is
+referenced when ksmbd server thread terminates, It will not be freed,
+but conn->tcp_transport is freed. __smb2_lease_break_noti can be performed
+asynchronously when the connection is disconnected. __smb2_lease_break_noti
+calls ksmbd_conn_write, which can cause use-after-free
+when conn->ksmbd_transport is already freed.
+
+Cc: stable@vger.kernel.org
+Reported-by: Norbert Szetei <norbert@doyensec.com>
+Tested-by: Norbert Szetei <norbert@doyensec.com>
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/smb/server/connection.c | 4 +++-
+ fs/smb/server/transport_tcp.c | 14 +++++++++-----
+ fs/smb/server/transport_tcp.h | 1 +
+ 3 files changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/fs/smb/server/connection.c b/fs/smb/server/connection.c
+index b0f69cee96a75..7aaea71a4f206 100644
+--- a/fs/smb/server/connection.c
++++ b/fs/smb/server/connection.c
+@@ -39,8 +39,10 @@ void ksmbd_conn_free(struct ksmbd_conn *conn)
+ xa_destroy(&conn->sessions);
+ kvfree(conn->request_buf);
+ kfree(conn->preauth_info);
+- if (atomic_dec_and_test(&conn->refcnt))
++ if (atomic_dec_and_test(&conn->refcnt)) {
++ ksmbd_free_transport(conn->transport);
+ kfree(conn);
++ }
+ }
+
+ /**
+diff --git a/fs/smb/server/transport_tcp.c b/fs/smb/server/transport_tcp.c
+index 7f38a3c3f5bd6..abedf510899a7 100644
+--- a/fs/smb/server/transport_tcp.c
++++ b/fs/smb/server/transport_tcp.c
+@@ -93,17 +93,21 @@ static struct tcp_transport *alloc_transport(struct socket *client_sk)
+ return t;
+ }
+
+-static void free_transport(struct tcp_transport *t)
++void ksmbd_free_transport(struct ksmbd_transport *kt)
+ {
+- kernel_sock_shutdown(t->sock, SHUT_RDWR);
+- sock_release(t->sock);
+- t->sock = NULL;
++ struct tcp_transport *t = TCP_TRANS(kt);
+
+- ksmbd_conn_free(KSMBD_TRANS(t)->conn);
++ sock_release(t->sock);
+ kfree(t->iov);
+ kfree(t);
+ }
+
++static void free_transport(struct tcp_transport *t)
++{
++ kernel_sock_shutdown(t->sock, SHUT_RDWR);
++ ksmbd_conn_free(KSMBD_TRANS(t)->conn);
++}
++
+ /**
+ * kvec_array_init() - initialize a IO vector segment
+ * @new: IO vector to be initialized
+diff --git a/fs/smb/server/transport_tcp.h b/fs/smb/server/transport_tcp.h
+index 8c9aa624cfe3c..1e51675ee1b20 100644
+--- a/fs/smb/server/transport_tcp.h
++++ b/fs/smb/server/transport_tcp.h
+@@ -8,6 +8,7 @@
+
+ int ksmbd_tcp_set_interfaces(char *ifc_list, int ifc_list_sz);
+ struct interface *ksmbd_find_netdev_name_iface_list(char *netdev_name);
++void ksmbd_free_transport(struct ksmbd_transport *kt);
+ int ksmbd_tcp_init(void);
+ void ksmbd_tcp_destroy(void);
+
+--
+2.39.5
+
--- /dev/null
+From 0edc31ea0dd342b8caa49a7e59c2ea68b354b78c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 22 Nov 2024 16:33:25 +0900
+Subject: ksmbd: use __GFP_RETRY_MAYFAIL
+
+From: Namjae Jeon <linkinjeon@kernel.org>
+
+[ Upstream commit 0066f623bce8f98b69b752ee03d46a5047c281b8 ]
+
+Prefer to report ENOMEM rather than incur the oom for allocations in
+ksmbd. __GFP_NORETRY could not achieve that, It would fail the allocations
+just too easily. __GFP_RETRY_MAYFAIL will keep retrying the allocation
+until there is no more progress and fail the allocation instead go OOM
+and let the caller to deal with it.
+
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Stable-dep-of: 21a4e47578d4 ("ksmbd: fix use-after-free in __smb2_lease_break_noti()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/smb/server/asn1.c | 6 ++---
+ fs/smb/server/auth.c | 19 ++++++++--------
+ fs/smb/server/connection.c | 4 ++--
+ fs/smb/server/crypto_ctx.c | 6 ++---
+ fs/smb/server/glob.h | 2 ++
+ fs/smb/server/ksmbd_work.c | 10 ++++----
+ fs/smb/server/mgmt/ksmbd_ida.c | 11 +++++----
+ fs/smb/server/mgmt/share_config.c | 10 ++++----
+ fs/smb/server/mgmt/tree_connect.c | 5 ++--
+ fs/smb/server/mgmt/user_config.c | 8 +++----
+ fs/smb/server/mgmt/user_session.c | 10 ++++----
+ fs/smb/server/misc.c | 11 +++++----
+ fs/smb/server/ndr.c | 10 ++++----
+ fs/smb/server/oplock.c | 12 +++++-----
+ fs/smb/server/server.c | 4 ++--
+ fs/smb/server/smb2pdu.c | 38 +++++++++++++++----------------
+ fs/smb/server/smb_common.c | 2 +-
+ fs/smb/server/smbacl.c | 23 ++++++++++---------
+ fs/smb/server/transport_ipc.c | 6 ++---
+ fs/smb/server/transport_rdma.c | 10 ++++----
+ fs/smb/server/transport_tcp.c | 12 +++++-----
+ fs/smb/server/unicode.c | 4 ++--
+ fs/smb/server/vfs.c | 12 +++++-----
+ fs/smb/server/vfs_cache.c | 10 ++++----
+ 24 files changed, 126 insertions(+), 119 deletions(-)
+
+diff --git a/fs/smb/server/asn1.c b/fs/smb/server/asn1.c
+index b931a99ab9c85..5c4c5121fece1 100644
+--- a/fs/smb/server/asn1.c
++++ b/fs/smb/server/asn1.c
+@@ -104,7 +104,7 @@ int build_spnego_ntlmssp_neg_blob(unsigned char **pbuffer, u16 *buflen,
+ oid_len + ntlmssp_len) * 2 +
+ neg_result_len + oid_len + ntlmssp_len;
+
+- buf = kmalloc(total_len, GFP_KERNEL);
++ buf = kmalloc(total_len, KSMBD_DEFAULT_GFP);
+ if (!buf)
+ return -ENOMEM;
+
+@@ -140,7 +140,7 @@ int build_spnego_ntlmssp_auth_blob(unsigned char **pbuffer, u16 *buflen,
+ int total_len = 4 + compute_asn_hdr_len_bytes(neg_result_len) * 2 +
+ neg_result_len;
+
+- buf = kmalloc(total_len, GFP_KERNEL);
++ buf = kmalloc(total_len, KSMBD_DEFAULT_GFP);
+ if (!buf)
+ return -ENOMEM;
+
+@@ -217,7 +217,7 @@ static int ksmbd_neg_token_alloc(void *context, size_t hdrlen,
+ if (!vlen)
+ return -EINVAL;
+
+- conn->mechToken = kmemdup_nul(value, vlen, GFP_KERNEL);
++ conn->mechToken = kmemdup_nul(value, vlen, KSMBD_DEFAULT_GFP);
+ if (!conn->mechToken)
+ return -ENOMEM;
+
+diff --git a/fs/smb/server/auth.c b/fs/smb/server/auth.c
+index 9544975136831..83caa38497493 100644
+--- a/fs/smb/server/auth.c
++++ b/fs/smb/server/auth.c
+@@ -151,7 +151,7 @@ static int calc_ntlmv2_hash(struct ksmbd_conn *conn, struct ksmbd_session *sess,
+
+ /* convert user_name to unicode */
+ len = strlen(user_name(sess->user));
+- uniname = kzalloc(2 + UNICODE_LEN(len), GFP_KERNEL);
++ uniname = kzalloc(2 + UNICODE_LEN(len), KSMBD_DEFAULT_GFP);
+ if (!uniname) {
+ ret = -ENOMEM;
+ goto out;
+@@ -175,7 +175,7 @@ static int calc_ntlmv2_hash(struct ksmbd_conn *conn, struct ksmbd_session *sess,
+
+ /* Convert domain name or conn name to unicode and uppercase */
+ len = strlen(dname);
+- domain = kzalloc(2 + UNICODE_LEN(len), GFP_KERNEL);
++ domain = kzalloc(2 + UNICODE_LEN(len), KSMBD_DEFAULT_GFP);
+ if (!domain) {
+ ret = -ENOMEM;
+ goto out;
+@@ -254,7 +254,7 @@ int ksmbd_auth_ntlmv2(struct ksmbd_conn *conn, struct ksmbd_session *sess,
+ }
+
+ len = CIFS_CRYPTO_KEY_SIZE + blen;
+- construct = kzalloc(len, GFP_KERNEL);
++ construct = kzalloc(len, KSMBD_DEFAULT_GFP);
+ if (!construct) {
+ rc = -ENOMEM;
+ goto out;
+@@ -361,7 +361,7 @@ int ksmbd_decode_ntlmssp_auth_blob(struct authenticate_message *authblob,
+ if (sess_key_len > CIFS_KEY_SIZE)
+ return -EINVAL;
+
+- ctx_arc4 = kmalloc(sizeof(*ctx_arc4), GFP_KERNEL);
++ ctx_arc4 = kmalloc(sizeof(*ctx_arc4), KSMBD_DEFAULT_GFP);
+ if (!ctx_arc4)
+ return -ENOMEM;
+
+@@ -451,7 +451,7 @@ ksmbd_build_ntlmssp_challenge_blob(struct challenge_message *chgblob,
+
+ chgblob->NegotiateFlags = cpu_to_le32(flags);
+ len = strlen(ksmbd_netbios_name());
+- name = kmalloc(2 + UNICODE_LEN(len), GFP_KERNEL);
++ name = kmalloc(2 + UNICODE_LEN(len), KSMBD_DEFAULT_GFP);
+ if (!name)
+ return -ENOMEM;
+
+@@ -1045,7 +1045,7 @@ static struct scatterlist *ksmbd_init_sg(struct kvec *iov, unsigned int nvec,
+ if (!nvec)
+ return NULL;
+
+- nr_entries = kcalloc(nvec, sizeof(int), GFP_KERNEL);
++ nr_entries = kcalloc(nvec, sizeof(int), KSMBD_DEFAULT_GFP);
+ if (!nr_entries)
+ return NULL;
+
+@@ -1065,7 +1065,8 @@ static struct scatterlist *ksmbd_init_sg(struct kvec *iov, unsigned int nvec,
+ /* Add two entries for transform header and signature */
+ total_entries += 2;
+
+- sg = kmalloc_array(total_entries, sizeof(struct scatterlist), GFP_KERNEL);
++ sg = kmalloc_array(total_entries, sizeof(struct scatterlist),
++ KSMBD_DEFAULT_GFP);
+ if (!sg) {
+ kfree(nr_entries);
+ return NULL;
+@@ -1165,7 +1166,7 @@ int ksmbd_crypt_message(struct ksmbd_work *work, struct kvec *iov,
+ goto free_ctx;
+ }
+
+- req = aead_request_alloc(tfm, GFP_KERNEL);
++ req = aead_request_alloc(tfm, KSMBD_DEFAULT_GFP);
+ if (!req) {
+ rc = -ENOMEM;
+ goto free_ctx;
+@@ -1184,7 +1185,7 @@ int ksmbd_crypt_message(struct ksmbd_work *work, struct kvec *iov,
+ }
+
+ iv_len = crypto_aead_ivsize(tfm);
+- iv = kzalloc(iv_len, GFP_KERNEL);
++ iv = kzalloc(iv_len, KSMBD_DEFAULT_GFP);
+ if (!iv) {
+ rc = -ENOMEM;
+ goto free_sg;
+diff --git a/fs/smb/server/connection.c b/fs/smb/server/connection.c
+index ab11246ccd8a0..b0f69cee96a75 100644
+--- a/fs/smb/server/connection.c
++++ b/fs/smb/server/connection.c
+@@ -52,7 +52,7 @@ struct ksmbd_conn *ksmbd_conn_alloc(void)
+ {
+ struct ksmbd_conn *conn;
+
+- conn = kzalloc(sizeof(struct ksmbd_conn), GFP_KERNEL);
++ conn = kzalloc(sizeof(struct ksmbd_conn), KSMBD_DEFAULT_GFP);
+ if (!conn)
+ return NULL;
+
+@@ -369,7 +369,7 @@ int ksmbd_conn_handler_loop(void *p)
+ /* 4 for rfc1002 length field */
+ /* 1 for implied bcc[0] */
+ size = pdu_size + 4 + 1;
+- conn->request_buf = kvmalloc(size, GFP_KERNEL);
++ conn->request_buf = kvmalloc(size, KSMBD_DEFAULT_GFP);
+ if (!conn->request_buf)
+ break;
+
+diff --git a/fs/smb/server/crypto_ctx.c b/fs/smb/server/crypto_ctx.c
+index 81488d04199da..ce733dc9a4a35 100644
+--- a/fs/smb/server/crypto_ctx.c
++++ b/fs/smb/server/crypto_ctx.c
+@@ -89,7 +89,7 @@ static struct shash_desc *alloc_shash_desc(int id)
+ return NULL;
+
+ shash = kzalloc(sizeof(*shash) + crypto_shash_descsize(tfm),
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!shash)
+ crypto_free_shash(tfm);
+ else
+@@ -133,7 +133,7 @@ static struct ksmbd_crypto_ctx *ksmbd_find_crypto_ctx(void)
+ ctx_list.avail_ctx++;
+ spin_unlock(&ctx_list.ctx_lock);
+
+- ctx = kzalloc(sizeof(struct ksmbd_crypto_ctx), GFP_KERNEL);
++ ctx = kzalloc(sizeof(struct ksmbd_crypto_ctx), KSMBD_DEFAULT_GFP);
+ if (!ctx) {
+ spin_lock(&ctx_list.ctx_lock);
+ ctx_list.avail_ctx--;
+@@ -258,7 +258,7 @@ int ksmbd_crypto_create(void)
+ init_waitqueue_head(&ctx_list.ctx_wait);
+ ctx_list.avail_ctx = 1;
+
+- ctx = kzalloc(sizeof(struct ksmbd_crypto_ctx), GFP_KERNEL);
++ ctx = kzalloc(sizeof(struct ksmbd_crypto_ctx), KSMBD_DEFAULT_GFP);
+ if (!ctx)
+ return -ENOMEM;
+ list_add(&ctx->list, &ctx_list.idle_ctx);
+diff --git a/fs/smb/server/glob.h b/fs/smb/server/glob.h
+index d528b20b37a85..4ea187af23480 100644
+--- a/fs/smb/server/glob.h
++++ b/fs/smb/server/glob.h
+@@ -44,4 +44,6 @@ extern int ksmbd_debug_types;
+
+ #define UNICODE_LEN(x) ((x) * 2)
+
++#define KSMBD_DEFAULT_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL)
++
+ #endif /* __KSMBD_GLOB_H */
+diff --git a/fs/smb/server/ksmbd_work.c b/fs/smb/server/ksmbd_work.c
+index 544d8ccd29b0a..72b00ca6e4551 100644
+--- a/fs/smb/server/ksmbd_work.c
++++ b/fs/smb/server/ksmbd_work.c
+@@ -18,7 +18,7 @@ static struct workqueue_struct *ksmbd_wq;
+
+ struct ksmbd_work *ksmbd_alloc_work_struct(void)
+ {
+- struct ksmbd_work *work = kmem_cache_zalloc(work_cache, GFP_KERNEL);
++ struct ksmbd_work *work = kmem_cache_zalloc(work_cache, KSMBD_DEFAULT_GFP);
+
+ if (work) {
+ work->compound_fid = KSMBD_NO_FID;
+@@ -29,7 +29,7 @@ struct ksmbd_work *ksmbd_alloc_work_struct(void)
+ INIT_LIST_HEAD(&work->aux_read_list);
+ work->iov_alloc_cnt = 4;
+ work->iov = kcalloc(work->iov_alloc_cnt, sizeof(struct kvec),
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!work->iov) {
+ kmem_cache_free(work_cache, work);
+ work = NULL;
+@@ -111,7 +111,7 @@ static int __ksmbd_iov_pin_rsp(struct ksmbd_work *work, void *ib, int len,
+
+ if (aux_size) {
+ need_iov_cnt++;
+- ar = kmalloc(sizeof(struct aux_read), GFP_KERNEL);
++ ar = kmalloc(sizeof(struct aux_read), KSMBD_DEFAULT_GFP);
+ if (!ar)
+ return -ENOMEM;
+ }
+@@ -122,7 +122,7 @@ static int __ksmbd_iov_pin_rsp(struct ksmbd_work *work, void *ib, int len,
+ work->iov_alloc_cnt += 4;
+ new = krealloc(work->iov,
+ sizeof(struct kvec) * work->iov_alloc_cnt,
+- GFP_KERNEL | __GFP_ZERO);
++ KSMBD_DEFAULT_GFP | __GFP_ZERO);
+ if (!new) {
+ kfree(ar);
+ work->iov_alloc_cnt -= 4;
+@@ -166,7 +166,7 @@ int ksmbd_iov_pin_rsp_read(struct ksmbd_work *work, void *ib, int len,
+
+ int allocate_interim_rsp_buf(struct ksmbd_work *work)
+ {
+- work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE, GFP_KERNEL);
++ work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE, KSMBD_DEFAULT_GFP);
+ if (!work->response_buf)
+ return -ENOMEM;
+ work->response_sz = MAX_CIFS_SMALL_BUFFER_SIZE;
+diff --git a/fs/smb/server/mgmt/ksmbd_ida.c b/fs/smb/server/mgmt/ksmbd_ida.c
+index a18e27e9e0cd9..0e2ae994ab525 100644
+--- a/fs/smb/server/mgmt/ksmbd_ida.c
++++ b/fs/smb/server/mgmt/ksmbd_ida.c
+@@ -4,31 +4,32 @@
+ */
+
+ #include "ksmbd_ida.h"
++#include "../glob.h"
+
+ int ksmbd_acquire_smb2_tid(struct ida *ida)
+ {
+- return ida_alloc_range(ida, 1, 0xFFFFFFFE, GFP_KERNEL);
++ return ida_alloc_range(ida, 1, 0xFFFFFFFE, KSMBD_DEFAULT_GFP);
+ }
+
+ int ksmbd_acquire_smb2_uid(struct ida *ida)
+ {
+ int id;
+
+- id = ida_alloc_min(ida, 1, GFP_KERNEL);
++ id = ida_alloc_min(ida, 1, KSMBD_DEFAULT_GFP);
+ if (id == 0xFFFE)
+- id = ida_alloc_min(ida, 1, GFP_KERNEL);
++ id = ida_alloc_min(ida, 1, KSMBD_DEFAULT_GFP);
+
+ return id;
+ }
+
+ int ksmbd_acquire_async_msg_id(struct ida *ida)
+ {
+- return ida_alloc_min(ida, 1, GFP_KERNEL);
++ return ida_alloc_min(ida, 1, KSMBD_DEFAULT_GFP);
+ }
+
+ int ksmbd_acquire_id(struct ida *ida)
+ {
+- return ida_alloc(ida, GFP_KERNEL);
++ return ida_alloc(ida, KSMBD_DEFAULT_GFP);
+ }
+
+ void ksmbd_release_id(struct ida *ida, int id)
+diff --git a/fs/smb/server/mgmt/share_config.c b/fs/smb/server/mgmt/share_config.c
+index d8d03070ae44b..d3d5f99bdd34e 100644
+--- a/fs/smb/server/mgmt/share_config.c
++++ b/fs/smb/server/mgmt/share_config.c
+@@ -102,11 +102,11 @@ static int parse_veto_list(struct ksmbd_share_config *share,
+ if (!sz)
+ break;
+
+- p = kzalloc(sizeof(struct ksmbd_veto_pattern), GFP_KERNEL);
++ p = kzalloc(sizeof(struct ksmbd_veto_pattern), KSMBD_DEFAULT_GFP);
+ if (!p)
+ return -ENOMEM;
+
+- p->pattern = kstrdup(veto_list, GFP_KERNEL);
++ p->pattern = kstrdup(veto_list, KSMBD_DEFAULT_GFP);
+ if (!p->pattern) {
+ kfree(p);
+ return -ENOMEM;
+@@ -150,14 +150,14 @@ static struct ksmbd_share_config *share_config_request(struct ksmbd_work *work,
+ goto out;
+ }
+
+- share = kzalloc(sizeof(struct ksmbd_share_config), GFP_KERNEL);
++ share = kzalloc(sizeof(struct ksmbd_share_config), KSMBD_DEFAULT_GFP);
+ if (!share)
+ goto out;
+
+ share->flags = resp->flags;
+ atomic_set(&share->refcount, 1);
+ INIT_LIST_HEAD(&share->veto_list);
+- share->name = kstrdup(name, GFP_KERNEL);
++ share->name = kstrdup(name, KSMBD_DEFAULT_GFP);
+
+ if (!test_share_config_flag(share, KSMBD_SHARE_FLAG_PIPE)) {
+ int path_len = PATH_MAX;
+@@ -166,7 +166,7 @@ static struct ksmbd_share_config *share_config_request(struct ksmbd_work *work,
+ path_len = resp->payload_sz - resp->veto_list_sz;
+
+ share->path = kstrndup(ksmbd_share_config_path(resp), path_len,
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (share->path) {
+ share->path_sz = strlen(share->path);
+ while (share->path_sz > 1 &&
+diff --git a/fs/smb/server/mgmt/tree_connect.c b/fs/smb/server/mgmt/tree_connect.c
+index 94a52a75014a4..ecfc575086712 100644
+--- a/fs/smb/server/mgmt/tree_connect.c
++++ b/fs/smb/server/mgmt/tree_connect.c
+@@ -31,7 +31,8 @@ ksmbd_tree_conn_connect(struct ksmbd_work *work, const char *share_name)
+ if (!sc)
+ return status;
+
+- tree_conn = kzalloc(sizeof(struct ksmbd_tree_connect), GFP_KERNEL);
++ tree_conn = kzalloc(sizeof(struct ksmbd_tree_connect),
++ KSMBD_DEFAULT_GFP);
+ if (!tree_conn) {
+ status.ret = -ENOMEM;
+ goto out_error;
+@@ -80,7 +81,7 @@ ksmbd_tree_conn_connect(struct ksmbd_work *work, const char *share_name)
+ init_waitqueue_head(&tree_conn->refcount_q);
+
+ ret = xa_err(xa_store(&sess->tree_conns, tree_conn->id, tree_conn,
+- GFP_KERNEL));
++ KSMBD_DEFAULT_GFP));
+ if (ret) {
+ status.ret = -ENOMEM;
+ goto out_error;
+diff --git a/fs/smb/server/mgmt/user_config.c b/fs/smb/server/mgmt/user_config.c
+index 421a4a95e216a..56c9a38ca8789 100644
+--- a/fs/smb/server/mgmt/user_config.c
++++ b/fs/smb/server/mgmt/user_config.c
+@@ -36,16 +36,16 @@ struct ksmbd_user *ksmbd_alloc_user(struct ksmbd_login_response *resp,
+ {
+ struct ksmbd_user *user;
+
+- user = kmalloc(sizeof(struct ksmbd_user), GFP_KERNEL);
++ user = kmalloc(sizeof(struct ksmbd_user), KSMBD_DEFAULT_GFP);
+ if (!user)
+ return NULL;
+
+- user->name = kstrdup(resp->account, GFP_KERNEL);
++ user->name = kstrdup(resp->account, KSMBD_DEFAULT_GFP);
+ user->flags = resp->status;
+ user->gid = resp->gid;
+ user->uid = resp->uid;
+ user->passkey_sz = resp->hash_sz;
+- user->passkey = kmalloc(resp->hash_sz, GFP_KERNEL);
++ user->passkey = kmalloc(resp->hash_sz, KSMBD_DEFAULT_GFP);
+ if (user->passkey)
+ memcpy(user->passkey, resp->hash, resp->hash_sz);
+
+@@ -64,7 +64,7 @@ struct ksmbd_user *ksmbd_alloc_user(struct ksmbd_login_response *resp,
+
+ user->sgid = kmemdup(resp_ext->____payload,
+ resp_ext->ngroups * sizeof(gid_t),
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!user->sgid)
+ goto err_free;
+
+diff --git a/fs/smb/server/mgmt/user_session.c b/fs/smb/server/mgmt/user_session.c
+index f83daf72f877e..3f45f28f6f0f8 100644
+--- a/fs/smb/server/mgmt/user_session.c
++++ b/fs/smb/server/mgmt/user_session.c
+@@ -98,7 +98,7 @@ int ksmbd_session_rpc_open(struct ksmbd_session *sess, char *rpc_name)
+ if (!method)
+ return -EINVAL;
+
+- entry = kzalloc(sizeof(struct ksmbd_session_rpc), GFP_KERNEL);
++ entry = kzalloc(sizeof(struct ksmbd_session_rpc), KSMBD_DEFAULT_GFP);
+ if (!entry)
+ return -ENOMEM;
+
+@@ -106,7 +106,7 @@ int ksmbd_session_rpc_open(struct ksmbd_session *sess, char *rpc_name)
+ entry->id = ksmbd_ipc_id_alloc();
+ if (entry->id < 0)
+ goto free_entry;
+- old = xa_store(&sess->rpc_handle_list, entry->id, entry, GFP_KERNEL);
++ old = xa_store(&sess->rpc_handle_list, entry->id, entry, KSMBD_DEFAULT_GFP);
+ if (xa_is_err(old))
+ goto free_id;
+
+@@ -201,7 +201,7 @@ int ksmbd_session_register(struct ksmbd_conn *conn,
+ sess->dialect = conn->dialect;
+ memcpy(sess->ClientGUID, conn->ClientGUID, SMB2_CLIENT_GUID_SIZE);
+ ksmbd_expire_session(conn);
+- return xa_err(xa_store(&conn->sessions, sess->id, sess, GFP_KERNEL));
++ return xa_err(xa_store(&conn->sessions, sess->id, sess, KSMBD_DEFAULT_GFP));
+ }
+
+ static int ksmbd_chann_del(struct ksmbd_conn *conn, struct ksmbd_session *sess)
+@@ -339,7 +339,7 @@ struct preauth_session *ksmbd_preauth_session_alloc(struct ksmbd_conn *conn,
+ {
+ struct preauth_session *sess;
+
+- sess = kmalloc(sizeof(struct preauth_session), GFP_KERNEL);
++ sess = kmalloc(sizeof(struct preauth_session), KSMBD_DEFAULT_GFP);
+ if (!sess)
+ return NULL;
+
+@@ -423,7 +423,7 @@ static struct ksmbd_session *__session_create(int protocol)
+ if (protocol != CIFDS_SESSION_FLAG_SMB2)
+ return NULL;
+
+- sess = kzalloc(sizeof(struct ksmbd_session), GFP_KERNEL);
++ sess = kzalloc(sizeof(struct ksmbd_session), KSMBD_DEFAULT_GFP);
+ if (!sess)
+ return NULL;
+
+diff --git a/fs/smb/server/misc.c b/fs/smb/server/misc.c
+index 1a5faa6f6e7bc..cb2a11ffb23fe 100644
+--- a/fs/smb/server/misc.c
++++ b/fs/smb/server/misc.c
+@@ -165,7 +165,7 @@ char *convert_to_nt_pathname(struct ksmbd_share_config *share,
+ char *pathname, *ab_pathname, *nt_pathname;
+ int share_path_len = share->path_sz;
+
+- pathname = kmalloc(PATH_MAX, GFP_KERNEL);
++ pathname = kmalloc(PATH_MAX, KSMBD_DEFAULT_GFP);
+ if (!pathname)
+ return ERR_PTR(-EACCES);
+
+@@ -180,7 +180,8 @@ char *convert_to_nt_pathname(struct ksmbd_share_config *share,
+ goto free_pathname;
+ }
+
+- nt_pathname = kzalloc(strlen(&ab_pathname[share_path_len]) + 2, GFP_KERNEL);
++ nt_pathname = kzalloc(strlen(&ab_pathname[share_path_len]) + 2,
++ KSMBD_DEFAULT_GFP);
+ if (!nt_pathname) {
+ nt_pathname = ERR_PTR(-ENOMEM);
+ goto free_pathname;
+@@ -232,7 +233,7 @@ char *ksmbd_casefold_sharename(struct unicode_map *um, const char *name)
+ char *cf_name;
+ int cf_len;
+
+- cf_name = kzalloc(KSMBD_REQ_MAX_SHARE_NAME, GFP_KERNEL);
++ cf_name = kzalloc(KSMBD_REQ_MAX_SHARE_NAME, KSMBD_DEFAULT_GFP);
+ if (!cf_name)
+ return ERR_PTR(-ENOMEM);
+
+@@ -294,7 +295,7 @@ char *convert_to_unix_name(struct ksmbd_share_config *share, const char *name)
+
+ path_len = share->path_sz;
+ name_len = strlen(name);
+- new_name = kmalloc(path_len + name_len + 2, GFP_KERNEL);
++ new_name = kmalloc(path_len + name_len + 2, KSMBD_DEFAULT_GFP);
+ if (!new_name)
+ return new_name;
+
+@@ -320,7 +321,7 @@ char *ksmbd_convert_dir_info_name(struct ksmbd_dir_info *d_info,
+ if (!sz)
+ return NULL;
+
+- conv = kmalloc(sz, GFP_KERNEL);
++ conv = kmalloc(sz, KSMBD_DEFAULT_GFP);
+ if (!conv)
+ return NULL;
+
+diff --git a/fs/smb/server/ndr.c b/fs/smb/server/ndr.c
+index 3507d8f890749..58d71560f626b 100644
+--- a/fs/smb/server/ndr.c
++++ b/fs/smb/server/ndr.c
+@@ -18,7 +18,7 @@ static int try_to_realloc_ndr_blob(struct ndr *n, size_t sz)
+ {
+ char *data;
+
+- data = krealloc(n->data, n->offset + sz + 1024, GFP_KERNEL);
++ data = krealloc(n->data, n->offset + sz + 1024, KSMBD_DEFAULT_GFP);
+ if (!data)
+ return -ENOMEM;
+
+@@ -174,7 +174,7 @@ int ndr_encode_dos_attr(struct ndr *n, struct xattr_dos_attrib *da)
+
+ n->offset = 0;
+ n->length = 1024;
+- n->data = kzalloc(n->length, GFP_KERNEL);
++ n->data = kzalloc(n->length, KSMBD_DEFAULT_GFP);
+ if (!n->data)
+ return -ENOMEM;
+
+@@ -350,7 +350,7 @@ int ndr_encode_posix_acl(struct ndr *n,
+
+ n->offset = 0;
+ n->length = 1024;
+- n->data = kzalloc(n->length, GFP_KERNEL);
++ n->data = kzalloc(n->length, KSMBD_DEFAULT_GFP);
+ if (!n->data)
+ return -ENOMEM;
+
+@@ -401,7 +401,7 @@ int ndr_encode_v4_ntacl(struct ndr *n, struct xattr_ntacl *acl)
+
+ n->offset = 0;
+ n->length = 2048;
+- n->data = kzalloc(n->length, GFP_KERNEL);
++ n->data = kzalloc(n->length, KSMBD_DEFAULT_GFP);
+ if (!n->data)
+ return -ENOMEM;
+
+@@ -505,7 +505,7 @@ int ndr_decode_v4_ntacl(struct ndr *n, struct xattr_ntacl *acl)
+ return ret;
+
+ acl->sd_size = n->length - n->offset;
+- acl->sd_buf = kzalloc(acl->sd_size, GFP_KERNEL);
++ acl->sd_buf = kzalloc(acl->sd_size, KSMBD_DEFAULT_GFP);
+ if (!acl->sd_buf)
+ return -ENOMEM;
+
+diff --git a/fs/smb/server/oplock.c b/fs/smb/server/oplock.c
+index e2ba0dadb5fbf..81a29857b1e32 100644
+--- a/fs/smb/server/oplock.c
++++ b/fs/smb/server/oplock.c
+@@ -34,7 +34,7 @@ static struct oplock_info *alloc_opinfo(struct ksmbd_work *work,
+ struct ksmbd_session *sess = work->sess;
+ struct oplock_info *opinfo;
+
+- opinfo = kzalloc(sizeof(struct oplock_info), GFP_KERNEL);
++ opinfo = kzalloc(sizeof(struct oplock_info), KSMBD_DEFAULT_GFP);
+ if (!opinfo)
+ return NULL;
+
+@@ -93,7 +93,7 @@ static int alloc_lease(struct oplock_info *opinfo, struct lease_ctx_info *lctx)
+ {
+ struct lease *lease;
+
+- lease = kmalloc(sizeof(struct lease), GFP_KERNEL);
++ lease = kmalloc(sizeof(struct lease), KSMBD_DEFAULT_GFP);
+ if (!lease)
+ return -ENOMEM;
+
+@@ -701,7 +701,7 @@ static int smb2_oplock_break_noti(struct oplock_info *opinfo)
+ if (!work)
+ return -ENOMEM;
+
+- br_info = kmalloc(sizeof(struct oplock_break_info), GFP_KERNEL);
++ br_info = kmalloc(sizeof(struct oplock_break_info), KSMBD_DEFAULT_GFP);
+ if (!br_info) {
+ ksmbd_free_work_struct(work);
+ return -ENOMEM;
+@@ -806,7 +806,7 @@ static int smb2_lease_break_noti(struct oplock_info *opinfo)
+ if (!work)
+ return -ENOMEM;
+
+- br_info = kmalloc(sizeof(struct lease_break_info), GFP_KERNEL);
++ br_info = kmalloc(sizeof(struct lease_break_info), KSMBD_DEFAULT_GFP);
+ if (!br_info) {
+ ksmbd_free_work_struct(work);
+ return -ENOMEM;
+@@ -1049,7 +1049,7 @@ static int add_lease_global_list(struct oplock_info *opinfo)
+ }
+ read_unlock(&lease_list_lock);
+
+- lb = kmalloc(sizeof(struct lease_table), GFP_KERNEL);
++ lb = kmalloc(sizeof(struct lease_table), KSMBD_DEFAULT_GFP);
+ if (!lb)
+ return -ENOMEM;
+
+@@ -1487,7 +1487,7 @@ struct lease_ctx_info *parse_lease_state(void *open_req)
+ if (IS_ERR_OR_NULL(cc))
+ return NULL;
+
+- lreq = kzalloc(sizeof(struct lease_ctx_info), GFP_KERNEL);
++ lreq = kzalloc(sizeof(struct lease_ctx_info), KSMBD_DEFAULT_GFP);
+ if (!lreq)
+ return NULL;
+
+diff --git a/fs/smb/server/server.c b/fs/smb/server/server.c
+index d523b860236ab..ab533c6029879 100644
+--- a/fs/smb/server/server.c
++++ b/fs/smb/server/server.c
+@@ -47,7 +47,7 @@ static int ___server_conf_set(int idx, char *val)
+ return -EINVAL;
+
+ kfree(server_conf.conf[idx]);
+- server_conf.conf[idx] = kstrdup(val, GFP_KERNEL);
++ server_conf.conf[idx] = kstrdup(val, KSMBD_DEFAULT_GFP);
+ if (!server_conf.conf[idx])
+ return -ENOMEM;
+ return 0;
+@@ -404,7 +404,7 @@ static int __queue_ctrl_work(int type)
+ {
+ struct server_ctrl_struct *ctrl;
+
+- ctrl = kmalloc(sizeof(struct server_ctrl_struct), GFP_KERNEL);
++ ctrl = kmalloc(sizeof(struct server_ctrl_struct), KSMBD_DEFAULT_GFP);
+ if (!ctrl)
+ return -ENOMEM;
+
+diff --git a/fs/smb/server/smb2pdu.c b/fs/smb/server/smb2pdu.c
+index 129517a0c5c73..dfae37951312f 100644
+--- a/fs/smb/server/smb2pdu.c
++++ b/fs/smb/server/smb2pdu.c
+@@ -553,7 +553,7 @@ int smb2_allocate_rsp_buf(struct ksmbd_work *work)
+ if (le32_to_cpu(hdr->NextCommand) > 0)
+ sz = large_sz;
+
+- work->response_buf = kvzalloc(sz, GFP_KERNEL);
++ work->response_buf = kvzalloc(sz, KSMBD_DEFAULT_GFP);
+ if (!work->response_buf)
+ return -ENOMEM;
+
+@@ -1150,7 +1150,7 @@ int smb2_handle_negotiate(struct ksmbd_work *work)
+ case SMB311_PROT_ID:
+ conn->preauth_info =
+ kzalloc(sizeof(struct preauth_integrity_info),
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!conn->preauth_info) {
+ rc = -ENOMEM;
+ rsp->hdr.Status = STATUS_INVALID_PARAMETER;
+@@ -1272,7 +1272,7 @@ static int alloc_preauth_hash(struct ksmbd_session *sess,
+ return -ENOMEM;
+
+ sess->Preauth_HashValue = kmemdup(conn->preauth_info->Preauth_HashValue,
+- PREAUTH_HASHVALUE_SIZE, GFP_KERNEL);
++ PREAUTH_HASHVALUE_SIZE, KSMBD_DEFAULT_GFP);
+ if (!sess->Preauth_HashValue)
+ return -ENOMEM;
+
+@@ -1358,7 +1358,7 @@ static int ntlm_negotiate(struct ksmbd_work *work,
+ sz = sizeof(struct challenge_message);
+ sz += (strlen(ksmbd_netbios_name()) * 2 + 1 + 4) * 6;
+
+- neg_blob = kzalloc(sz, GFP_KERNEL);
++ neg_blob = kzalloc(sz, KSMBD_DEFAULT_GFP);
+ if (!neg_blob)
+ return -ENOMEM;
+
+@@ -1549,12 +1549,12 @@ static int ntlm_authenticate(struct ksmbd_work *work,
+ if (conn->dialect >= SMB30_PROT_ID) {
+ chann = lookup_chann_list(sess, conn);
+ if (!chann) {
+- chann = kmalloc(sizeof(struct channel), GFP_KERNEL);
++ chann = kmalloc(sizeof(struct channel), KSMBD_DEFAULT_GFP);
+ if (!chann)
+ return -ENOMEM;
+
+ chann->conn = conn;
+- xa_store(&sess->ksmbd_chann_list, (long)conn, chann, GFP_KERNEL);
++ xa_store(&sess->ksmbd_chann_list, (long)conn, chann, KSMBD_DEFAULT_GFP);
+ }
+ }
+
+@@ -1632,12 +1632,12 @@ static int krb5_authenticate(struct ksmbd_work *work,
+ if (conn->dialect >= SMB30_PROT_ID) {
+ chann = lookup_chann_list(sess, conn);
+ if (!chann) {
+- chann = kmalloc(sizeof(struct channel), GFP_KERNEL);
++ chann = kmalloc(sizeof(struct channel), KSMBD_DEFAULT_GFP);
+ if (!chann)
+ return -ENOMEM;
+
+ chann->conn = conn;
+- xa_store(&sess->ksmbd_chann_list, (long)conn, chann, GFP_KERNEL);
++ xa_store(&sess->ksmbd_chann_list, (long)conn, chann, KSMBD_DEFAULT_GFP);
+ }
+ }
+
+@@ -2356,7 +2356,7 @@ static int smb2_set_ea(struct smb2_ea_info *eabuf, unsigned int buf_len,
+ le16_to_cpu(eabuf->EaValueLength))
+ return -EINVAL;
+
+- attr_name = kmalloc(XATTR_NAME_MAX + 1, GFP_KERNEL);
++ attr_name = kmalloc(XATTR_NAME_MAX + 1, KSMBD_DEFAULT_GFP);
+ if (!attr_name)
+ return -ENOMEM;
+
+@@ -2928,7 +2928,7 @@ int smb2_open(struct ksmbd_work *work)
+ goto err_out2;
+ }
+ } else {
+- name = kstrdup("", GFP_KERNEL);
++ name = kstrdup("", KSMBD_DEFAULT_GFP);
+ if (!name) {
+ rc = -ENOMEM;
+ goto err_out2;
+@@ -3369,7 +3369,7 @@ int smb2_open(struct ksmbd_work *work)
+ sizeof(struct smb_sid) * 3 +
+ sizeof(struct smb_acl) +
+ sizeof(struct smb_ace) * ace_num * 2,
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!pntsd) {
+ posix_acl_release(fattr.cf_acls);
+ posix_acl_release(fattr.cf_dacls);
+@@ -5007,7 +5007,7 @@ static int get_file_stream_info(struct ksmbd_work *work,
+
+ /* plus : size */
+ streamlen += 1;
+- stream_buf = kmalloc(streamlen + 1, GFP_KERNEL);
++ stream_buf = kmalloc(streamlen + 1, KSMBD_DEFAULT_GFP);
+ if (!stream_buf)
+ break;
+
+@@ -6002,7 +6002,7 @@ static int smb2_create_link(struct ksmbd_work *work,
+ return -EINVAL;
+
+ ksmbd_debug(SMB, "setting FILE_LINK_INFORMATION\n");
+- pathname = kmalloc(PATH_MAX, GFP_KERNEL);
++ pathname = kmalloc(PATH_MAX, KSMBD_DEFAULT_GFP);
+ if (!pathname)
+ return -ENOMEM;
+
+@@ -6562,7 +6562,7 @@ static noinline int smb2_read_pipe(struct ksmbd_work *work)
+ }
+
+ aux_payload_buf =
+- kvmalloc(rpc_resp->payload_sz, GFP_KERNEL);
++ kvmalloc(rpc_resp->payload_sz, KSMBD_DEFAULT_GFP);
+ if (!aux_payload_buf) {
+ err = -ENOMEM;
+ goto out;
+@@ -6745,7 +6745,7 @@ int smb2_read(struct ksmbd_work *work)
+ ksmbd_debug(SMB, "filename %pD, offset %lld, len %zu\n",
+ fp->filp, offset, length);
+
+- aux_payload_buf = kvzalloc(length, GFP_KERNEL);
++ aux_payload_buf = kvzalloc(length, KSMBD_DEFAULT_GFP);
+ if (!aux_payload_buf) {
+ err = -ENOMEM;
+ goto out;
+@@ -6897,7 +6897,7 @@ static ssize_t smb2_write_rdma_channel(struct ksmbd_work *work,
+ int ret;
+ ssize_t nbytes;
+
+- data_buf = kvzalloc(length, GFP_KERNEL);
++ data_buf = kvzalloc(length, KSMBD_DEFAULT_GFP);
+ if (!data_buf)
+ return -ENOMEM;
+
+@@ -7228,7 +7228,7 @@ static struct ksmbd_lock *smb2_lock_init(struct file_lock *flock,
+ {
+ struct ksmbd_lock *lock;
+
+- lock = kzalloc(sizeof(struct ksmbd_lock), GFP_KERNEL);
++ lock = kzalloc(sizeof(struct ksmbd_lock), KSMBD_DEFAULT_GFP);
+ if (!lock)
+ return NULL;
+
+@@ -7496,7 +7496,7 @@ int smb2_lock(struct ksmbd_work *work)
+ "would have to wait for getting lock\n");
+ list_add(&smb_lock->llist, &rollback_list);
+
+- argv = kmalloc(sizeof(void *), GFP_KERNEL);
++ argv = kmalloc(sizeof(void *), KSMBD_DEFAULT_GFP);
+ if (!argv) {
+ err = -ENOMEM;
+ goto out;
+@@ -8990,7 +8990,7 @@ int smb3_encrypt_resp(struct ksmbd_work *work)
+ int rc = -ENOMEM;
+ void *tr_buf;
+
+- tr_buf = kzalloc(sizeof(struct smb2_transform_hdr) + 4, GFP_KERNEL);
++ tr_buf = kzalloc(sizeof(struct smb2_transform_hdr) + 4, KSMBD_DEFAULT_GFP);
+ if (!tr_buf)
+ return rc;
+
+diff --git a/fs/smb/server/smb_common.c b/fs/smb/server/smb_common.c
+index af8e24163bf26..191df59748e00 100644
+--- a/fs/smb/server/smb_common.c
++++ b/fs/smb/server/smb_common.c
+@@ -358,7 +358,7 @@ static int smb1_check_user_session(struct ksmbd_work *work)
+ static int smb1_allocate_rsp_buf(struct ksmbd_work *work)
+ {
+ work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE,
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ work->response_sz = MAX_CIFS_SMALL_BUFFER_SIZE;
+
+ if (!work->response_buf) {
+diff --git a/fs/smb/server/smbacl.c b/fs/smb/server/smbacl.c
+index 376ae68144afa..5aa7a66334d93 100644
+--- a/fs/smb/server/smbacl.c
++++ b/fs/smb/server/smbacl.c
+@@ -350,10 +350,10 @@ int init_acl_state(struct posix_acl_state *state, u16 cnt)
+ */
+ alloc = sizeof(struct posix_ace_state_array)
+ + cnt * sizeof(struct posix_user_ace_state);
+- state->users = kzalloc(alloc, GFP_KERNEL);
++ state->users = kzalloc(alloc, KSMBD_DEFAULT_GFP);
+ if (!state->users)
+ return -ENOMEM;
+- state->groups = kzalloc(alloc, GFP_KERNEL);
++ state->groups = kzalloc(alloc, KSMBD_DEFAULT_GFP);
+ if (!state->groups) {
+ kfree(state->users);
+ return -ENOMEM;
+@@ -417,7 +417,7 @@ static void parse_dacl(struct mnt_idmap *idmap,
+ return;
+ }
+
+- ppace = kmalloc_array(num_aces, sizeof(struct smb_ace *), GFP_KERNEL);
++ ppace = kmalloc_array(num_aces, sizeof(struct smb_ace *), KSMBD_DEFAULT_GFP);
+ if (!ppace) {
+ free_acl_state(&default_acl_state);
+ free_acl_state(&acl_state);
+@@ -561,7 +561,7 @@ static void parse_dacl(struct mnt_idmap *idmap,
+ if (IS_ENABLED(CONFIG_FS_POSIX_ACL)) {
+ fattr->cf_acls =
+ posix_acl_alloc(acl_state.users->n +
+- acl_state.groups->n + 4, GFP_KERNEL);
++ acl_state.groups->n + 4, KSMBD_DEFAULT_GFP);
+ if (fattr->cf_acls) {
+ cf_pace = fattr->cf_acls->a_entries;
+ posix_state_to_acl(&acl_state, cf_pace);
+@@ -575,7 +575,7 @@ static void parse_dacl(struct mnt_idmap *idmap,
+ if (IS_ENABLED(CONFIG_FS_POSIX_ACL)) {
+ fattr->cf_dacls =
+ posix_acl_alloc(default_acl_state.users->n +
+- default_acl_state.groups->n + 4, GFP_KERNEL);
++ default_acl_state.groups->n + 4, KSMBD_DEFAULT_GFP);
+ if (fattr->cf_dacls) {
+ cf_pdace = fattr->cf_dacls->a_entries;
+ posix_state_to_acl(&default_acl_state, cf_pdace);
+@@ -603,7 +603,7 @@ static void set_posix_acl_entries_dacl(struct mnt_idmap *idmap,
+ for (i = 0; i < fattr->cf_acls->a_count; i++, pace++) {
+ int flags = 0;
+
+- sid = kmalloc(sizeof(struct smb_sid), GFP_KERNEL);
++ sid = kmalloc(sizeof(struct smb_sid), KSMBD_DEFAULT_GFP);
+ if (!sid)
+ break;
+
+@@ -670,7 +670,7 @@ static void set_posix_acl_entries_dacl(struct mnt_idmap *idmap,
+
+ pace = fattr->cf_dacls->a_entries;
+ for (i = 0; i < fattr->cf_dacls->a_count; i++, pace++) {
+- sid = kmalloc(sizeof(struct smb_sid), GFP_KERNEL);
++ sid = kmalloc(sizeof(struct smb_sid), KSMBD_DEFAULT_GFP);
+ if (!sid)
+ break;
+
+@@ -930,7 +930,7 @@ int build_sec_desc(struct mnt_idmap *idmap,
+ gid_t gid;
+ unsigned int sid_type = SIDOWNER;
+
+- nowner_sid_ptr = kmalloc(sizeof(struct smb_sid), GFP_KERNEL);
++ nowner_sid_ptr = kmalloc(sizeof(struct smb_sid), KSMBD_DEFAULT_GFP);
+ if (!nowner_sid_ptr)
+ return -ENOMEM;
+
+@@ -939,7 +939,7 @@ int build_sec_desc(struct mnt_idmap *idmap,
+ sid_type = SIDUNIX_USER;
+ id_to_sid(uid, sid_type, nowner_sid_ptr);
+
+- ngroup_sid_ptr = kmalloc(sizeof(struct smb_sid), GFP_KERNEL);
++ ngroup_sid_ptr = kmalloc(sizeof(struct smb_sid), KSMBD_DEFAULT_GFP);
+ if (!ngroup_sid_ptr) {
+ kfree(nowner_sid_ptr);
+ return -ENOMEM;
+@@ -1062,7 +1062,8 @@ int smb_inherit_dacl(struct ksmbd_conn *conn,
+ goto free_parent_pntsd;
+ }
+
+- aces_base = kmalloc(sizeof(struct smb_ace) * num_aces * 2, GFP_KERNEL);
++ aces_base = kmalloc(sizeof(struct smb_ace) * num_aces * 2,
++ KSMBD_DEFAULT_GFP);
+ if (!aces_base) {
+ rc = -ENOMEM;
+ goto free_parent_pntsd;
+@@ -1156,7 +1157,7 @@ int smb_inherit_dacl(struct ksmbd_conn *conn,
+ pntsd_alloc_size = sizeof(struct smb_ntsd) + powner_sid_size +
+ pgroup_sid_size + sizeof(struct smb_acl) + nt_size;
+
+- pntsd = kzalloc(pntsd_alloc_size, GFP_KERNEL);
++ pntsd = kzalloc(pntsd_alloc_size, KSMBD_DEFAULT_GFP);
+ if (!pntsd) {
+ rc = -ENOMEM;
+ goto free_aces_base;
+diff --git a/fs/smb/server/transport_ipc.c b/fs/smb/server/transport_ipc.c
+index 9b3c68014aee2..2e17164efc91a 100644
+--- a/fs/smb/server/transport_ipc.c
++++ b/fs/smb/server/transport_ipc.c
+@@ -244,7 +244,7 @@ static struct ksmbd_ipc_msg *ipc_msg_alloc(size_t sz)
+ struct ksmbd_ipc_msg *msg;
+ size_t msg_sz = sz + sizeof(struct ksmbd_ipc_msg);
+
+- msg = kvzalloc(msg_sz, GFP_KERNEL);
++ msg = kvzalloc(msg_sz, KSMBD_DEFAULT_GFP);
+ if (msg)
+ msg->sz = sz;
+ return msg;
+@@ -284,7 +284,7 @@ static int handle_response(int type, void *payload, size_t sz)
+ continue;
+ }
+
+- entry->response = kvzalloc(sz, GFP_KERNEL);
++ entry->response = kvzalloc(sz, KSMBD_DEFAULT_GFP);
+ if (!entry->response) {
+ ret = -ENOMEM;
+ break;
+@@ -453,7 +453,7 @@ static int ipc_msg_send(struct ksmbd_ipc_msg *msg)
+ if (!ksmbd_tools_pid)
+ return ret;
+
+- skb = genlmsg_new(msg->sz, GFP_KERNEL);
++ skb = genlmsg_new(msg->sz, KSMBD_DEFAULT_GFP);
+ if (!skb)
+ return -ENOMEM;
+
+diff --git a/fs/smb/server/transport_rdma.c b/fs/smb/server/transport_rdma.c
+index 17c76713c6d08..7c5a0d712873d 100644
+--- a/fs/smb/server/transport_rdma.c
++++ b/fs/smb/server/transport_rdma.c
+@@ -362,7 +362,7 @@ static struct smb_direct_transport *alloc_transport(struct rdma_cm_id *cm_id)
+ struct smb_direct_transport *t;
+ struct ksmbd_conn *conn;
+
+- t = kzalloc(sizeof(*t), GFP_KERNEL);
++ t = kzalloc(sizeof(*t), KSMBD_DEFAULT_GFP);
+ if (!t)
+ return NULL;
+
+@@ -462,7 +462,7 @@ static struct smb_direct_sendmsg
+ {
+ struct smb_direct_sendmsg *msg;
+
+- msg = mempool_alloc(t->sendmsg_mempool, GFP_KERNEL);
++ msg = mempool_alloc(t->sendmsg_mempool, KSMBD_DEFAULT_GFP);
+ if (!msg)
+ return ERR_PTR(-ENOMEM);
+ msg->transport = t;
+@@ -1406,7 +1406,7 @@ static int smb_direct_rdma_xmit(struct smb_direct_transport *t,
+ desc_buf = buf;
+ for (i = 0; i < desc_num; i++) {
+ msg = kzalloc(struct_size(msg, sg_list, SG_CHUNK_SIZE),
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!msg) {
+ ret = -ENOMEM;
+ goto out;
+@@ -1852,7 +1852,7 @@ static int smb_direct_create_pools(struct smb_direct_transport *t)
+ INIT_LIST_HEAD(&t->recvmsg_queue);
+
+ for (i = 0; i < t->recv_credit_max; i++) {
+- recvmsg = mempool_alloc(t->recvmsg_mempool, GFP_KERNEL);
++ recvmsg = mempool_alloc(t->recvmsg_mempool, KSMBD_DEFAULT_GFP);
+ if (!recvmsg)
+ goto err;
+ recvmsg->transport = t;
+@@ -2144,7 +2144,7 @@ static int smb_direct_ib_client_add(struct ib_device *ib_dev)
+ if (!rdma_frwr_is_supported(&ib_dev->attrs))
+ return 0;
+
+- smb_dev = kzalloc(sizeof(*smb_dev), GFP_KERNEL);
++ smb_dev = kzalloc(sizeof(*smb_dev), KSMBD_DEFAULT_GFP);
+ if (!smb_dev)
+ return -ENOMEM;
+ smb_dev->ib_dev = ib_dev;
+diff --git a/fs/smb/server/transport_tcp.c b/fs/smb/server/transport_tcp.c
+index aaed9e293b2e0..cc77ad4f765a9 100644
+--- a/fs/smb/server/transport_tcp.c
++++ b/fs/smb/server/transport_tcp.c
+@@ -76,7 +76,7 @@ static struct tcp_transport *alloc_transport(struct socket *client_sk)
+ struct tcp_transport *t;
+ struct ksmbd_conn *conn;
+
+- t = kzalloc(sizeof(*t), GFP_KERNEL);
++ t = kzalloc(sizeof(*t), KSMBD_DEFAULT_GFP);
+ if (!t)
+ return NULL;
+ t->sock = client_sk;
+@@ -151,7 +151,7 @@ static struct kvec *get_conn_iovec(struct tcp_transport *t, unsigned int nr_segs
+ return t->iov;
+
+ /* not big enough -- allocate a new one and release the old */
+- new_iov = kmalloc_array(nr_segs, sizeof(*new_iov), GFP_KERNEL);
++ new_iov = kmalloc_array(nr_segs, sizeof(*new_iov), KSMBD_DEFAULT_GFP);
+ if (new_iov) {
+ kfree(t->iov);
+ t->iov = new_iov;
+@@ -528,7 +528,7 @@ static int ksmbd_netdev_event(struct notifier_block *nb, unsigned long event,
+ }
+ }
+ if (!found && bind_additional_ifaces) {
+- iface = alloc_iface(kstrdup(netdev->name, GFP_KERNEL));
++ iface = alloc_iface(kstrdup(netdev->name, KSMBD_DEFAULT_GFP));
+ if (!iface)
+ return NOTIFY_OK;
+ ret = create_socket(iface);
+@@ -600,7 +600,7 @@ static struct interface *alloc_iface(char *ifname)
+ if (!ifname)
+ return NULL;
+
+- iface = kzalloc(sizeof(struct interface), GFP_KERNEL);
++ iface = kzalloc(sizeof(struct interface), KSMBD_DEFAULT_GFP);
+ if (!iface) {
+ kfree(ifname);
+ return NULL;
+@@ -624,7 +624,7 @@ int ksmbd_tcp_set_interfaces(char *ifc_list, int ifc_list_sz)
+ for_each_netdev(&init_net, netdev) {
+ if (netif_is_bridge_port(netdev))
+ continue;
+- if (!alloc_iface(kstrdup(netdev->name, GFP_KERNEL))) {
++ if (!alloc_iface(kstrdup(netdev->name, KSMBD_DEFAULT_GFP))) {
+ rtnl_unlock();
+ return -ENOMEM;
+ }
+@@ -635,7 +635,7 @@ int ksmbd_tcp_set_interfaces(char *ifc_list, int ifc_list_sz)
+ }
+
+ while (ifc_list_sz > 0) {
+- if (!alloc_iface(kstrdup(ifc_list, GFP_KERNEL)))
++ if (!alloc_iface(kstrdup(ifc_list, KSMBD_DEFAULT_GFP)))
+ return -ENOMEM;
+
+ sz = strlen(ifc_list);
+diff --git a/fs/smb/server/unicode.c b/fs/smb/server/unicode.c
+index 217106ff7b828..85e6791745ec8 100644
+--- a/fs/smb/server/unicode.c
++++ b/fs/smb/server/unicode.c
+@@ -297,7 +297,7 @@ char *smb_strndup_from_utf16(const char *src, const int maxlen,
+ if (is_unicode) {
+ len = smb_utf16_bytes((__le16 *)src, maxlen, codepage);
+ len += nls_nullsize(codepage);
+- dst = kmalloc(len, GFP_KERNEL);
++ dst = kmalloc(len, KSMBD_DEFAULT_GFP);
+ if (!dst)
+ return ERR_PTR(-ENOMEM);
+ ret = smb_from_utf16(dst, (__le16 *)src, len, maxlen, codepage,
+@@ -309,7 +309,7 @@ char *smb_strndup_from_utf16(const char *src, const int maxlen,
+ } else {
+ len = strnlen(src, maxlen);
+ len++;
+- dst = kmalloc(len, GFP_KERNEL);
++ dst = kmalloc(len, KSMBD_DEFAULT_GFP);
+ if (!dst)
+ return ERR_PTR(-ENOMEM);
+ strscpy(dst, src, len);
+diff --git a/fs/smb/server/vfs.c b/fs/smb/server/vfs.c
+index 8fd070e31fa7d..a7694aae0b947 100644
+--- a/fs/smb/server/vfs.c
++++ b/fs/smb/server/vfs.c
+@@ -444,7 +444,7 @@ static int ksmbd_vfs_stream_write(struct ksmbd_file *fp, char *buf, loff_t *pos,
+ }
+
+ if (v_len < size) {
+- wbuf = kvzalloc(size, GFP_KERNEL);
++ wbuf = kvzalloc(size, KSMBD_DEFAULT_GFP);
+ if (!wbuf) {
+ err = -ENOMEM;
+ goto out;
+@@ -866,7 +866,7 @@ ssize_t ksmbd_vfs_listxattr(struct dentry *dentry, char **list)
+ if (size <= 0)
+ return size;
+
+- vlist = kvzalloc(size, GFP_KERNEL);
++ vlist = kvzalloc(size, KSMBD_DEFAULT_GFP);
+ if (!vlist)
+ return -ENOMEM;
+
+@@ -908,7 +908,7 @@ ssize_t ksmbd_vfs_getxattr(struct mnt_idmap *idmap,
+ if (xattr_len < 0)
+ return xattr_len;
+
+- buf = kmalloc(xattr_len + 1, GFP_KERNEL);
++ buf = kmalloc(xattr_len + 1, KSMBD_DEFAULT_GFP);
+ if (!buf)
+ return -ENOMEM;
+
+@@ -1413,7 +1413,7 @@ static struct xattr_smb_acl *ksmbd_vfs_make_xattr_posix_acl(struct mnt_idmap *id
+
+ smb_acl = kzalloc(sizeof(struct xattr_smb_acl) +
+ sizeof(struct xattr_acl_entry) * posix_acls->a_count,
+- GFP_KERNEL);
++ KSMBD_DEFAULT_GFP);
+ if (!smb_acl)
+ goto out;
+
+@@ -1769,7 +1769,7 @@ int ksmbd_vfs_xattr_stream_name(char *stream_name, char **xattr_stream_name,
+ else
+ type = ":$DATA";
+
+- buf = kasprintf(GFP_KERNEL, "%s%s%s",
++ buf = kasprintf(KSMBD_DEFAULT_GFP, "%s%s%s",
+ XATTR_NAME_STREAM, stream_name, type);
+ if (!buf)
+ return -ENOMEM;
+@@ -1898,7 +1898,7 @@ int ksmbd_vfs_set_init_posix_acl(struct mnt_idmap *idmap,
+ acl_state.group.allow;
+ acl_state.mask.allow = 0x07;
+
+- acls = posix_acl_alloc(6, GFP_KERNEL);
++ acls = posix_acl_alloc(6, KSMBD_DEFAULT_GFP);
+ if (!acls) {
+ free_acl_state(&acl_state);
+ return -ENOMEM;
+diff --git a/fs/smb/server/vfs_cache.c b/fs/smb/server/vfs_cache.c
+index a19f4e563c7e5..8d1f30dcba7e8 100644
+--- a/fs/smb/server/vfs_cache.c
++++ b/fs/smb/server/vfs_cache.c
+@@ -188,7 +188,7 @@ static struct ksmbd_inode *ksmbd_inode_get(struct ksmbd_file *fp)
+ if (ci)
+ return ci;
+
+- ci = kmalloc(sizeof(struct ksmbd_inode), GFP_KERNEL);
++ ci = kmalloc(sizeof(struct ksmbd_inode), KSMBD_DEFAULT_GFP);
+ if (!ci)
+ return NULL;
+
+@@ -577,7 +577,7 @@ static int __open_id(struct ksmbd_file_table *ft, struct ksmbd_file *fp,
+ return -EMFILE;
+ }
+
+- idr_preload(GFP_KERNEL);
++ idr_preload(KSMBD_DEFAULT_GFP);
+ write_lock(&ft->lock);
+ ret = idr_alloc_cyclic(ft->idr, fp, 0, INT_MAX - 1, GFP_NOWAIT);
+ if (ret >= 0) {
+@@ -605,7 +605,7 @@ struct ksmbd_file *ksmbd_open_fd(struct ksmbd_work *work, struct file *filp)
+ struct ksmbd_file *fp;
+ int ret;
+
+- fp = kmem_cache_zalloc(filp_cache, GFP_KERNEL);
++ fp = kmem_cache_zalloc(filp_cache, KSMBD_DEFAULT_GFP);
+ if (!fp) {
+ pr_err("Failed to allocate memory\n");
+ return ERR_PTR(-ENOMEM);
+@@ -923,7 +923,7 @@ int ksmbd_validate_name_reconnect(struct ksmbd_share_config *share,
+ char *pathname, *ab_pathname;
+ int ret = 0;
+
+- pathname = kmalloc(PATH_MAX, GFP_KERNEL);
++ pathname = kmalloc(PATH_MAX, KSMBD_DEFAULT_GFP);
+ if (!pathname)
+ return -EACCES;
+
+@@ -983,7 +983,7 @@ int ksmbd_reopen_durable_fd(struct ksmbd_work *work, struct ksmbd_file *fp)
+
+ int ksmbd_init_file_table(struct ksmbd_file_table *ft)
+ {
+- ft->idr = kzalloc(sizeof(struct idr), GFP_KERNEL);
++ ft->idr = kzalloc(sizeof(struct idr), KSMBD_DEFAULT_GFP);
+ if (!ft->idr)
+ return -ENOMEM;
+
+--
+2.39.5
+
--- /dev/null
+From 2ea323443a3ac6a3ceabe0ed4dfa37d31d663c8e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 14 Apr 2025 15:00:59 -0700
+Subject: lib/Kconfig.ubsan: Remove 'default UBSAN' from UBSAN_INTEGER_WRAP
+
+From: Nathan Chancellor <nathan@kernel.org>
+
+[ Upstream commit cdc2e1d9d929d7f7009b3a5edca52388a2b0891f ]
+
+CONFIG_UBSAN_INTEGER_WRAP is 'default UBSAN', which is problematic for a
+couple of reasons.
+
+The first is that this sanitizer is under active development on the
+compiler side to come up with a solution that is maintainable on the
+compiler side and usable on the kernel side. As a result of this, there
+are many warnings when the sanitizer is enabled that have no clear path
+to resolution yet but users may see them and report them in the meantime.
+
+The second is that this option was renamed from
+CONFIG_UBSAN_SIGNED_WRAP, meaning that if a configuration has
+CONFIG_UBSAN=y but CONFIG_UBSAN_SIGNED_WRAP=n and it is upgraded via
+olddefconfig (common in non-interactive scenarios such as CI),
+CONFIG_UBSAN_INTEGER_WRAP will be silently enabled again.
+
+Remove 'default UBSAN' from CONFIG_UBSAN_INTEGER_WRAP until it is ready
+for regular usage and testing from a broader community than the folks
+actively working on the feature.
+
+Cc: stable@vger.kernel.org
+Fixes: 557f8c582a9b ("ubsan: Reintroduce signed overflow sanitizer")
+Signed-off-by: Nathan Chancellor <nathan@kernel.org>
+Link: https://lore.kernel.org/r/20250414-drop-default-ubsan-integer-wrap-v1-1-392522551d6b@kernel.org
+Signed-off-by: Kees Cook <kees@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ lib/Kconfig.ubsan | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/lib/Kconfig.ubsan b/lib/Kconfig.ubsan
+index 63e5622010e0f..37b2839bd442f 100644
+--- a/lib/Kconfig.ubsan
++++ b/lib/Kconfig.ubsan
+@@ -118,7 +118,6 @@ config UBSAN_UNREACHABLE
+
+ config UBSAN_INTEGER_WRAP
+ bool "Perform checking for integer arithmetic wrap-around"
+- default UBSAN
+ depends on !COMPILE_TEST
+ depends on $(cc-option,-fsanitize=signed-integer-overflow)
+ depends on $(cc-option,-fsanitize=unsigned-integer-overflow)
+--
+2.39.5
+
--- /dev/null
+From 90c443e63664e60ca18ecea34fe622657db233bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:05 +0100
+Subject: media: i2c: imx214: Check number of lanes from device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit 3d55f4eb03fce69f3a72615fe9c5ca171f7b846b ]
+
+The imx214 camera is capable of either two-lane or four-lane operation.
+
+Currently only the four-lane mode is supported, as proper pixel rates
+and link frequences for the two-lane mode are unknown.
+
+Acked-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: acc294519f17 ("media: i2c: imx214: Fix link frequency validation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/imx214.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index 8bac5a1f1cb18..fdc2dfb4ebcdd 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -197,7 +197,6 @@ struct imx214 {
+
+ /*From imx214_mode_tbls.h*/
+ static const struct cci_reg_sequence mode_4096x2304[] = {
+- { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE },
+ { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
+ { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
+ { IMX214_REG_EXPOSURE_RATIO, 1 },
+@@ -271,7 +270,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = {
+ };
+
+ static const struct cci_reg_sequence mode_1920x1080[] = {
+- { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE },
+ { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
+ { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
+ { IMX214_REG_EXPOSURE_RATIO, 1 },
+@@ -789,6 +787,13 @@ static int imx214_start_streaming(struct imx214 *imx214)
+ return ret;
+ }
+
++ ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE,
++ IMX214_CSI_4_LANE_MODE, NULL);
++ if (ret) {
++ dev_err(imx214->dev, "failed to configure lanes\n");
++ return ret;
++ }
++
+ state = v4l2_subdev_get_locked_active_state(&imx214->sd);
+ fmt = v4l2_subdev_state_get_format(state, 0);
+ mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes),
+@@ -953,6 +958,13 @@ static int imx214_parse_fwnode(struct device *dev)
+ goto done;
+ }
+
++ /* Check the number of MIPI CSI2 data lanes */
++ if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
++ ret = dev_err_probe(dev, -EINVAL,
++ "only 4 data lanes are currently supported\n");
++ goto done;
++ }
++
+ for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
+ if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
+ break;
+--
+2.39.5
+
--- /dev/null
+From d9cf4f761dbc3b37b45f760f9c5315d476806523 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:02 +0100
+Subject: media: i2c: imx214: Convert to CCI register access helpers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit 4f0aeba4f1556f829f09073bf267093c5b6f1821 ]
+
+Use the new common CCI register access helpers to replace the private
+register access helpers in the imx214 driver. This simplifies the driver
+by reducing the amount of code.
+
+Acked-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: acc294519f17 ("media: i2c: imx214: Fix link frequency validation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/Kconfig | 1 +
+ drivers/media/i2c/imx214.c | 672 +++++++++++++++++--------------------
+ 2 files changed, 310 insertions(+), 363 deletions(-)
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 8ba096b8ebca2..85ecb2aeefdbf 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -140,6 +140,7 @@ config VIDEO_IMX214
+ tristate "Sony IMX214 sensor support"
+ depends on GPIOLIB
+ select REGMAP_I2C
++ select V4L2_CCI_I2C
+ help
+ This is a Video4Linux2 sensor driver for the Sony
+ IMX214 camera.
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index db6cdc3b65e37..20d1ebebf13af 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -15,11 +15,12 @@
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <media/media-entity.h>
++#include <media/v4l2-cci.h>
+ #include <media/v4l2-ctrls.h>
+ #include <media/v4l2-fwnode.h>
+ #include <media/v4l2-subdev.h>
+
+-#define IMX214_REG_MODE_SELECT 0x0100
++#define IMX214_REG_MODE_SELECT CCI_REG8(0x0100)
+ #define IMX214_MODE_STANDBY 0x00
+ #define IMX214_MODE_STREAMING 0x01
+
+@@ -30,7 +31,7 @@
+ #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10
+
+ /* Exposure control */
+-#define IMX214_REG_EXPOSURE 0x0202
++#define IMX214_REG_EXPOSURE CCI_REG16(0x0202)
+ #define IMX214_EXPOSURE_MIN 0
+ #define IMX214_EXPOSURE_MAX 3184
+ #define IMX214_EXPOSURE_STEP 1
+@@ -71,345 +72,324 @@ struct imx214 {
+ struct gpio_desc *enable_gpio;
+ };
+
+-struct reg_8 {
+- u16 addr;
+- u8 val;
+-};
+-
+-enum {
+- IMX214_TABLE_WAIT_MS = 0,
+- IMX214_TABLE_END,
+- IMX214_MAX_RETRIES,
+- IMX214_WAIT_MS
+-};
+-
+ /*From imx214_mode_tbls.h*/
+-static const struct reg_8 mode_4096x2304[] = {
+- {0x0114, 0x03},
+- {0x0220, 0x00},
+- {0x0221, 0x11},
+- {0x0222, 0x01},
+- {0x0340, 0x0C},
+- {0x0341, 0x7A},
+- {0x0342, 0x13},
+- {0x0343, 0x90},
+- {0x0344, 0x00},
+- {0x0345, 0x38},
+- {0x0346, 0x01},
+- {0x0347, 0x98},
+- {0x0348, 0x10},
+- {0x0349, 0x37},
+- {0x034A, 0x0A},
+- {0x034B, 0x97},
+- {0x0381, 0x01},
+- {0x0383, 0x01},
+- {0x0385, 0x01},
+- {0x0387, 0x01},
+- {0x0900, 0x00},
+- {0x0901, 0x00},
+- {0x0902, 0x00},
+- {0x3000, 0x35},
+- {0x3054, 0x01},
+- {0x305C, 0x11},
+-
+- {0x0112, 0x0A},
+- {0x0113, 0x0A},
+- {0x034C, 0x10},
+- {0x034D, 0x00},
+- {0x034E, 0x09},
+- {0x034F, 0x00},
+- {0x0401, 0x00},
+- {0x0404, 0x00},
+- {0x0405, 0x10},
+- {0x0408, 0x00},
+- {0x0409, 0x00},
+- {0x040A, 0x00},
+- {0x040B, 0x00},
+- {0x040C, 0x10},
+- {0x040D, 0x00},
+- {0x040E, 0x09},
+- {0x040F, 0x00},
+-
+- {0x0301, 0x05},
+- {0x0303, 0x02},
+- {0x0305, 0x03},
+- {0x0306, 0x00},
+- {0x0307, 0x96},
+- {0x0309, 0x0A},
+- {0x030B, 0x01},
+- {0x0310, 0x00},
+-
+- {0x0820, 0x12},
+- {0x0821, 0xC0},
+- {0x0822, 0x00},
+- {0x0823, 0x00},
+-
+- {0x3A03, 0x09},
+- {0x3A04, 0x50},
+- {0x3A05, 0x01},
+-
+- {0x0B06, 0x01},
+- {0x30A2, 0x00},
+-
+- {0x30B4, 0x00},
+-
+- {0x3A02, 0xFF},
+-
+- {0x3011, 0x00},
+- {0x3013, 0x01},
+-
+- {0x0202, 0x0C},
+- {0x0203, 0x70},
+- {0x0224, 0x01},
+- {0x0225, 0xF4},
+-
+- {0x0204, 0x00},
+- {0x0205, 0x00},
+- {0x020E, 0x01},
+- {0x020F, 0x00},
+- {0x0210, 0x01},
+- {0x0211, 0x00},
+- {0x0212, 0x01},
+- {0x0213, 0x00},
+- {0x0214, 0x01},
+- {0x0215, 0x00},
+- {0x0216, 0x00},
+- {0x0217, 0x00},
+-
+- {0x4170, 0x00},
+- {0x4171, 0x10},
+- {0x4176, 0x00},
+- {0x4177, 0x3C},
+- {0xAE20, 0x04},
+- {0xAE21, 0x5C},
+-
+- {IMX214_TABLE_WAIT_MS, 10},
+- {0x0138, 0x01},
+- {IMX214_TABLE_END, 0x00}
++static const struct cci_reg_sequence mode_4096x2304[] = {
++ { CCI_REG8(0x0114), 0x03 },
++ { CCI_REG8(0x0220), 0x00 },
++ { CCI_REG8(0x0221), 0x11 },
++ { CCI_REG8(0x0222), 0x01 },
++ { CCI_REG8(0x0340), 0x0C },
++ { CCI_REG8(0x0341), 0x7A },
++ { CCI_REG8(0x0342), 0x13 },
++ { CCI_REG8(0x0343), 0x90 },
++ { CCI_REG8(0x0344), 0x00 },
++ { CCI_REG8(0x0345), 0x38 },
++ { CCI_REG8(0x0346), 0x01 },
++ { CCI_REG8(0x0347), 0x98 },
++ { CCI_REG8(0x0348), 0x10 },
++ { CCI_REG8(0x0349), 0x37 },
++ { CCI_REG8(0x034A), 0x0A },
++ { CCI_REG8(0x034B), 0x97 },
++ { CCI_REG8(0x0381), 0x01 },
++ { CCI_REG8(0x0383), 0x01 },
++ { CCI_REG8(0x0385), 0x01 },
++ { CCI_REG8(0x0387), 0x01 },
++ { CCI_REG8(0x0900), 0x00 },
++ { CCI_REG8(0x0901), 0x00 },
++ { CCI_REG8(0x0902), 0x00 },
++ { CCI_REG8(0x3000), 0x35 },
++ { CCI_REG8(0x3054), 0x01 },
++ { CCI_REG8(0x305C), 0x11 },
++
++ { CCI_REG8(0x0112), 0x0A },
++ { CCI_REG8(0x0113), 0x0A },
++ { CCI_REG8(0x034C), 0x10 },
++ { CCI_REG8(0x034D), 0x00 },
++ { CCI_REG8(0x034E), 0x09 },
++ { CCI_REG8(0x034F), 0x00 },
++ { CCI_REG8(0x0401), 0x00 },
++ { CCI_REG8(0x0404), 0x00 },
++ { CCI_REG8(0x0405), 0x10 },
++ { CCI_REG8(0x0408), 0x00 },
++ { CCI_REG8(0x0409), 0x00 },
++ { CCI_REG8(0x040A), 0x00 },
++ { CCI_REG8(0x040B), 0x00 },
++ { CCI_REG8(0x040C), 0x10 },
++ { CCI_REG8(0x040D), 0x00 },
++ { CCI_REG8(0x040E), 0x09 },
++ { CCI_REG8(0x040F), 0x00 },
++
++ { CCI_REG8(0x0301), 0x05 },
++ { CCI_REG8(0x0303), 0x02 },
++ { CCI_REG8(0x0305), 0x03 },
++ { CCI_REG8(0x0306), 0x00 },
++ { CCI_REG8(0x0307), 0x96 },
++ { CCI_REG8(0x0309), 0x0A },
++ { CCI_REG8(0x030B), 0x01 },
++ { CCI_REG8(0x0310), 0x00 },
++
++ { CCI_REG8(0x0820), 0x12 },
++ { CCI_REG8(0x0821), 0xC0 },
++ { CCI_REG8(0x0822), 0x00 },
++ { CCI_REG8(0x0823), 0x00 },
++
++ { CCI_REG8(0x3A03), 0x09 },
++ { CCI_REG8(0x3A04), 0x50 },
++ { CCI_REG8(0x3A05), 0x01 },
++
++ { CCI_REG8(0x0B06), 0x01 },
++ { CCI_REG8(0x30A2), 0x00 },
++
++ { CCI_REG8(0x30B4), 0x00 },
++
++ { CCI_REG8(0x3A02), 0xFF },
++
++ { CCI_REG8(0x3011), 0x00 },
++ { CCI_REG8(0x3013), 0x01 },
++
++ { CCI_REG8(0x0202), 0x0C },
++ { CCI_REG8(0x0203), 0x70 },
++ { CCI_REG8(0x0224), 0x01 },
++ { CCI_REG8(0x0225), 0xF4 },
++
++ { CCI_REG8(0x0204), 0x00 },
++ { CCI_REG8(0x0205), 0x00 },
++ { CCI_REG8(0x020E), 0x01 },
++ { CCI_REG8(0x020F), 0x00 },
++ { CCI_REG8(0x0210), 0x01 },
++ { CCI_REG8(0x0211), 0x00 },
++ { CCI_REG8(0x0212), 0x01 },
++ { CCI_REG8(0x0213), 0x00 },
++ { CCI_REG8(0x0214), 0x01 },
++ { CCI_REG8(0x0215), 0x00 },
++ { CCI_REG8(0x0216), 0x00 },
++ { CCI_REG8(0x0217), 0x00 },
++
++ { CCI_REG8(0x4170), 0x00 },
++ { CCI_REG8(0x4171), 0x10 },
++ { CCI_REG8(0x4176), 0x00 },
++ { CCI_REG8(0x4177), 0x3C },
++ { CCI_REG8(0xAE20), 0x04 },
++ { CCI_REG8(0xAE21), 0x5C },
+ };
+
+-static const struct reg_8 mode_1920x1080[] = {
+- {0x0114, 0x03},
+- {0x0220, 0x00},
+- {0x0221, 0x11},
+- {0x0222, 0x01},
+- {0x0340, 0x0C},
+- {0x0341, 0x7A},
+- {0x0342, 0x13},
+- {0x0343, 0x90},
+- {0x0344, 0x04},
+- {0x0345, 0x78},
+- {0x0346, 0x03},
+- {0x0347, 0xFC},
+- {0x0348, 0x0B},
+- {0x0349, 0xF7},
+- {0x034A, 0x08},
+- {0x034B, 0x33},
+- {0x0381, 0x01},
+- {0x0383, 0x01},
+- {0x0385, 0x01},
+- {0x0387, 0x01},
+- {0x0900, 0x00},
+- {0x0901, 0x00},
+- {0x0902, 0x00},
+- {0x3000, 0x35},
+- {0x3054, 0x01},
+- {0x305C, 0x11},
+-
+- {0x0112, 0x0A},
+- {0x0113, 0x0A},
+- {0x034C, 0x07},
+- {0x034D, 0x80},
+- {0x034E, 0x04},
+- {0x034F, 0x38},
+- {0x0401, 0x00},
+- {0x0404, 0x00},
+- {0x0405, 0x10},
+- {0x0408, 0x00},
+- {0x0409, 0x00},
+- {0x040A, 0x00},
+- {0x040B, 0x00},
+- {0x040C, 0x07},
+- {0x040D, 0x80},
+- {0x040E, 0x04},
+- {0x040F, 0x38},
+-
+- {0x0301, 0x05},
+- {0x0303, 0x02},
+- {0x0305, 0x03},
+- {0x0306, 0x00},
+- {0x0307, 0x96},
+- {0x0309, 0x0A},
+- {0x030B, 0x01},
+- {0x0310, 0x00},
+-
+- {0x0820, 0x12},
+- {0x0821, 0xC0},
+- {0x0822, 0x00},
+- {0x0823, 0x00},
+-
+- {0x3A03, 0x04},
+- {0x3A04, 0xF8},
+- {0x3A05, 0x02},
+-
+- {0x0B06, 0x01},
+- {0x30A2, 0x00},
+-
+- {0x30B4, 0x00},
+-
+- {0x3A02, 0xFF},
+-
+- {0x3011, 0x00},
+- {0x3013, 0x01},
+-
+- {0x0202, 0x0C},
+- {0x0203, 0x70},
+- {0x0224, 0x01},
+- {0x0225, 0xF4},
+-
+- {0x0204, 0x00},
+- {0x0205, 0x00},
+- {0x020E, 0x01},
+- {0x020F, 0x00},
+- {0x0210, 0x01},
+- {0x0211, 0x00},
+- {0x0212, 0x01},
+- {0x0213, 0x00},
+- {0x0214, 0x01},
+- {0x0215, 0x00},
+- {0x0216, 0x00},
+- {0x0217, 0x00},
+-
+- {0x4170, 0x00},
+- {0x4171, 0x10},
+- {0x4176, 0x00},
+- {0x4177, 0x3C},
+- {0xAE20, 0x04},
+- {0xAE21, 0x5C},
+-
+- {IMX214_TABLE_WAIT_MS, 10},
+- {0x0138, 0x01},
+- {IMX214_TABLE_END, 0x00}
++static const struct cci_reg_sequence mode_1920x1080[] = {
++ { CCI_REG8(0x0114), 0x03 },
++ { CCI_REG8(0x0220), 0x00 },
++ { CCI_REG8(0x0221), 0x11 },
++ { CCI_REG8(0x0222), 0x01 },
++ { CCI_REG8(0x0340), 0x0C },
++ { CCI_REG8(0x0341), 0x7A },
++ { CCI_REG8(0x0342), 0x13 },
++ { CCI_REG8(0x0343), 0x90 },
++ { CCI_REG8(0x0344), 0x04 },
++ { CCI_REG8(0x0345), 0x78 },
++ { CCI_REG8(0x0346), 0x03 },
++ { CCI_REG8(0x0347), 0xFC },
++ { CCI_REG8(0x0348), 0x0B },
++ { CCI_REG8(0x0349), 0xF7 },
++ { CCI_REG8(0x034A), 0x08 },
++ { CCI_REG8(0x034B), 0x33 },
++ { CCI_REG8(0x0381), 0x01 },
++ { CCI_REG8(0x0383), 0x01 },
++ { CCI_REG8(0x0385), 0x01 },
++ { CCI_REG8(0x0387), 0x01 },
++ { CCI_REG8(0x0900), 0x00 },
++ { CCI_REG8(0x0901), 0x00 },
++ { CCI_REG8(0x0902), 0x00 },
++ { CCI_REG8(0x3000), 0x35 },
++ { CCI_REG8(0x3054), 0x01 },
++ { CCI_REG8(0x305C), 0x11 },
++
++ { CCI_REG8(0x0112), 0x0A },
++ { CCI_REG8(0x0113), 0x0A },
++ { CCI_REG8(0x034C), 0x07 },
++ { CCI_REG8(0x034D), 0x80 },
++ { CCI_REG8(0x034E), 0x04 },
++ { CCI_REG8(0x034F), 0x38 },
++ { CCI_REG8(0x0401), 0x00 },
++ { CCI_REG8(0x0404), 0x00 },
++ { CCI_REG8(0x0405), 0x10 },
++ { CCI_REG8(0x0408), 0x00 },
++ { CCI_REG8(0x0409), 0x00 },
++ { CCI_REG8(0x040A), 0x00 },
++ { CCI_REG8(0x040B), 0x00 },
++ { CCI_REG8(0x040C), 0x07 },
++ { CCI_REG8(0x040D), 0x80 },
++ { CCI_REG8(0x040E), 0x04 },
++ { CCI_REG8(0x040F), 0x38 },
++
++ { CCI_REG8(0x0301), 0x05 },
++ { CCI_REG8(0x0303), 0x02 },
++ { CCI_REG8(0x0305), 0x03 },
++ { CCI_REG8(0x0306), 0x00 },
++ { CCI_REG8(0x0307), 0x96 },
++ { CCI_REG8(0x0309), 0x0A },
++ { CCI_REG8(0x030B), 0x01 },
++ { CCI_REG8(0x0310), 0x00 },
++
++ { CCI_REG8(0x0820), 0x12 },
++ { CCI_REG8(0x0821), 0xC0 },
++ { CCI_REG8(0x0822), 0x00 },
++ { CCI_REG8(0x0823), 0x00 },
++
++ { CCI_REG8(0x3A03), 0x04 },
++ { CCI_REG8(0x3A04), 0xF8 },
++ { CCI_REG8(0x3A05), 0x02 },
++
++ { CCI_REG8(0x0B06), 0x01 },
++ { CCI_REG8(0x30A2), 0x00 },
++
++ { CCI_REG8(0x30B4), 0x00 },
++
++ { CCI_REG8(0x3A02), 0xFF },
++
++ { CCI_REG8(0x3011), 0x00 },
++ { CCI_REG8(0x3013), 0x01 },
++
++ { CCI_REG8(0x0202), 0x0C },
++ { CCI_REG8(0x0203), 0x70 },
++ { CCI_REG8(0x0224), 0x01 },
++ { CCI_REG8(0x0225), 0xF4 },
++
++ { CCI_REG8(0x0204), 0x00 },
++ { CCI_REG8(0x0205), 0x00 },
++ { CCI_REG8(0x020E), 0x01 },
++ { CCI_REG8(0x020F), 0x00 },
++ { CCI_REG8(0x0210), 0x01 },
++ { CCI_REG8(0x0211), 0x00 },
++ { CCI_REG8(0x0212), 0x01 },
++ { CCI_REG8(0x0213), 0x00 },
++ { CCI_REG8(0x0214), 0x01 },
++ { CCI_REG8(0x0215), 0x00 },
++ { CCI_REG8(0x0216), 0x00 },
++ { CCI_REG8(0x0217), 0x00 },
++
++ { CCI_REG8(0x4170), 0x00 },
++ { CCI_REG8(0x4171), 0x10 },
++ { CCI_REG8(0x4176), 0x00 },
++ { CCI_REG8(0x4177), 0x3C },
++ { CCI_REG8(0xAE20), 0x04 },
++ { CCI_REG8(0xAE21), 0x5C },
+ };
+
+-static const struct reg_8 mode_table_common[] = {
++static const struct cci_reg_sequence mode_table_common[] = {
+ /* software reset */
+
+ /* software standby settings */
+- {0x0100, 0x00},
++ { CCI_REG8(0x0100), 0x00 },
+
+ /* ATR setting */
+- {0x9300, 0x02},
++ { CCI_REG8(0x9300), 0x02 },
+
+ /* external clock setting */
+- {0x0136, 0x18},
+- {0x0137, 0x00},
++ { CCI_REG8(0x0136), 0x18 },
++ { CCI_REG8(0x0137), 0x00 },
+
+ /* global setting */
+ /* basic config */
+- {0x0101, 0x00},
+- {0x0105, 0x01},
+- {0x0106, 0x01},
+- {0x4550, 0x02},
+- {0x4601, 0x00},
+- {0x4642, 0x05},
+- {0x6227, 0x11},
+- {0x6276, 0x00},
+- {0x900E, 0x06},
+- {0xA802, 0x90},
+- {0xA803, 0x11},
+- {0xA804, 0x62},
+- {0xA805, 0x77},
+- {0xA806, 0xAE},
+- {0xA807, 0x34},
+- {0xA808, 0xAE},
+- {0xA809, 0x35},
+- {0xA80A, 0x62},
+- {0xA80B, 0x83},
+- {0xAE33, 0x00},
++ { CCI_REG8(0x0101), 0x00 },
++ { CCI_REG8(0x0105), 0x01 },
++ { CCI_REG8(0x0106), 0x01 },
++ { CCI_REG8(0x4550), 0x02 },
++ { CCI_REG8(0x4601), 0x00 },
++ { CCI_REG8(0x4642), 0x05 },
++ { CCI_REG8(0x6227), 0x11 },
++ { CCI_REG8(0x6276), 0x00 },
++ { CCI_REG8(0x900E), 0x06 },
++ { CCI_REG8(0xA802), 0x90 },
++ { CCI_REG8(0xA803), 0x11 },
++ { CCI_REG8(0xA804), 0x62 },
++ { CCI_REG8(0xA805), 0x77 },
++ { CCI_REG8(0xA806), 0xAE },
++ { CCI_REG8(0xA807), 0x34 },
++ { CCI_REG8(0xA808), 0xAE },
++ { CCI_REG8(0xA809), 0x35 },
++ { CCI_REG8(0xA80A), 0x62 },
++ { CCI_REG8(0xA80B), 0x83 },
++ { CCI_REG8(0xAE33), 0x00 },
+
+ /* analog setting */
+- {0x4174, 0x00},
+- {0x4175, 0x11},
+- {0x4612, 0x29},
+- {0x461B, 0x12},
+- {0x461F, 0x06},
+- {0x4635, 0x07},
+- {0x4637, 0x30},
+- {0x463F, 0x18},
+- {0x4641, 0x0D},
+- {0x465B, 0x12},
+- {0x465F, 0x11},
+- {0x4663, 0x11},
+- {0x4667, 0x0F},
+- {0x466F, 0x0F},
+- {0x470E, 0x09},
+- {0x4909, 0xAB},
+- {0x490B, 0x95},
+- {0x4915, 0x5D},
+- {0x4A5F, 0xFF},
+- {0x4A61, 0xFF},
+- {0x4A73, 0x62},
+- {0x4A85, 0x00},
+- {0x4A87, 0xFF},
++ { CCI_REG8(0x4174), 0x00 },
++ { CCI_REG8(0x4175), 0x11 },
++ { CCI_REG8(0x4612), 0x29 },
++ { CCI_REG8(0x461B), 0x12 },
++ { CCI_REG8(0x461F), 0x06 },
++ { CCI_REG8(0x4635), 0x07 },
++ { CCI_REG8(0x4637), 0x30 },
++ { CCI_REG8(0x463F), 0x18 },
++ { CCI_REG8(0x4641), 0x0D },
++ { CCI_REG8(0x465B), 0x12 },
++ { CCI_REG8(0x465F), 0x11 },
++ { CCI_REG8(0x4663), 0x11 },
++ { CCI_REG8(0x4667), 0x0F },
++ { CCI_REG8(0x466F), 0x0F },
++ { CCI_REG8(0x470E), 0x09 },
++ { CCI_REG8(0x4909), 0xAB },
++ { CCI_REG8(0x490B), 0x95 },
++ { CCI_REG8(0x4915), 0x5D },
++ { CCI_REG8(0x4A5F), 0xFF },
++ { CCI_REG8(0x4A61), 0xFF },
++ { CCI_REG8(0x4A73), 0x62 },
++ { CCI_REG8(0x4A85), 0x00 },
++ { CCI_REG8(0x4A87), 0xFF },
+
+ /* embedded data */
+- {0x5041, 0x04},
+- {0x583C, 0x04},
+- {0x620E, 0x04},
+- {0x6EB2, 0x01},
+- {0x6EB3, 0x00},
+- {0x9300, 0x02},
++ { CCI_REG8(0x5041), 0x04 },
++ { CCI_REG8(0x583C), 0x04 },
++ { CCI_REG8(0x620E), 0x04 },
++ { CCI_REG8(0x6EB2), 0x01 },
++ { CCI_REG8(0x6EB3), 0x00 },
++ { CCI_REG8(0x9300), 0x02 },
+
+ /* imagequality */
+ /* HDR setting */
+- {0x3001, 0x07},
+- {0x6D12, 0x3F},
+- {0x6D13, 0xFF},
+- {0x9344, 0x03},
+- {0x9706, 0x10},
+- {0x9707, 0x03},
+- {0x9708, 0x03},
+- {0x9E04, 0x01},
+- {0x9E05, 0x00},
+- {0x9E0C, 0x01},
+- {0x9E0D, 0x02},
+- {0x9E24, 0x00},
+- {0x9E25, 0x8C},
+- {0x9E26, 0x00},
+- {0x9E27, 0x94},
+- {0x9E28, 0x00},
+- {0x9E29, 0x96},
++ { CCI_REG8(0x3001), 0x07 },
++ { CCI_REG8(0x6D12), 0x3F },
++ { CCI_REG8(0x6D13), 0xFF },
++ { CCI_REG8(0x9344), 0x03 },
++ { CCI_REG8(0x9706), 0x10 },
++ { CCI_REG8(0x9707), 0x03 },
++ { CCI_REG8(0x9708), 0x03 },
++ { CCI_REG8(0x9E04), 0x01 },
++ { CCI_REG8(0x9E05), 0x00 },
++ { CCI_REG8(0x9E0C), 0x01 },
++ { CCI_REG8(0x9E0D), 0x02 },
++ { CCI_REG8(0x9E24), 0x00 },
++ { CCI_REG8(0x9E25), 0x8C },
++ { CCI_REG8(0x9E26), 0x00 },
++ { CCI_REG8(0x9E27), 0x94 },
++ { CCI_REG8(0x9E28), 0x00 },
++ { CCI_REG8(0x9E29), 0x96 },
+
+ /* CNR parameter setting */
+- {0x69DB, 0x01},
++ { CCI_REG8(0x69DB), 0x01 },
+
+ /* Moire reduction */
+- {0x6957, 0x01},
++ { CCI_REG8(0x6957), 0x01 },
+
+ /* image enhancement */
+- {0x6987, 0x17},
+- {0x698A, 0x03},
+- {0x698B, 0x03},
++ { CCI_REG8(0x6987), 0x17 },
++ { CCI_REG8(0x698A), 0x03 },
++ { CCI_REG8(0x698B), 0x03 },
+
+ /* white balanace */
+- {0x0B8E, 0x01},
+- {0x0B8F, 0x00},
+- {0x0B90, 0x01},
+- {0x0B91, 0x00},
+- {0x0B92, 0x01},
+- {0x0B93, 0x00},
+- {0x0B94, 0x01},
+- {0x0B95, 0x00},
++ { CCI_REG8(0x0B8E), 0x01 },
++ { CCI_REG8(0x0B8F), 0x00 },
++ { CCI_REG8(0x0B90), 0x01 },
++ { CCI_REG8(0x0B91), 0x00 },
++ { CCI_REG8(0x0B92), 0x01 },
++ { CCI_REG8(0x0B93), 0x00 },
++ { CCI_REG8(0x0B94), 0x01 },
++ { CCI_REG8(0x0B95), 0x00 },
+
+ /* ATR setting */
+- {0x6E50, 0x00},
+- {0x6E51, 0x32},
+- {0x9340, 0x00},
+- {0x9341, 0x3C},
+- {0x9342, 0x03},
+- {0x9343, 0xFF},
+- {IMX214_TABLE_END, 0x00}
++ { CCI_REG8(0x6E50), 0x00 },
++ { CCI_REG8(0x6E51), 0x32 },
++ { CCI_REG8(0x9340), 0x00 },
++ { CCI_REG8(0x9341), 0x3C },
++ { CCI_REG8(0x9342), 0x03 },
++ { CCI_REG8(0x9343), 0xFF },
+ };
+
+ /*
+@@ -419,16 +399,19 @@ static const struct reg_8 mode_table_common[] = {
+ static const struct imx214_mode {
+ u32 width;
+ u32 height;
+- const struct reg_8 *reg_table;
++ unsigned int num_of_regs;
++ const struct cci_reg_sequence *reg_table;
+ } imx214_modes[] = {
+ {
+ .width = 4096,
+ .height = 2304,
++ .num_of_regs = ARRAY_SIZE(mode_4096x2304),
+ .reg_table = mode_4096x2304,
+ },
+ {
+ .width = 1920,
+ .height = 1080,
++ .num_of_regs = ARRAY_SIZE(mode_1920x1080),
+ .reg_table = mode_1920x1080,
+ },
+ };
+@@ -630,7 +613,6 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ struct imx214 *imx214 = container_of(ctrl->handler,
+ struct imx214, ctrls);
+- u8 vals[2];
+ int ret;
+
+ /*
+@@ -642,12 +624,7 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+- vals[1] = ctrl->val;
+- vals[0] = ctrl->val >> 8;
+- ret = regmap_bulk_write(imx214->regmap, IMX214_REG_EXPOSURE, vals, 2);
+- if (ret < 0)
+- dev_err(imx214->dev, "Error %d\n", ret);
+- ret = 0;
++ cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret);
+ break;
+
+ default:
+@@ -733,40 +710,6 @@ static int imx214_ctrls_init(struct imx214 *imx214)
+ return 0;
+ };
+
+-#define MAX_CMD 4
+-static int imx214_write_table(struct imx214 *imx214,
+- const struct reg_8 table[])
+-{
+- u8 vals[MAX_CMD];
+- int i;
+- int ret;
+-
+- for (; table->addr != IMX214_TABLE_END ; table++) {
+- if (table->addr == IMX214_TABLE_WAIT_MS) {
+- usleep_range(table->val * 1000,
+- table->val * 1000 + 500);
+- continue;
+- }
+-
+- for (i = 0; i < MAX_CMD; i++) {
+- if (table[i].addr != (table[0].addr + i))
+- break;
+- vals[i] = table[i].val;
+- }
+-
+- ret = regmap_bulk_write(imx214->regmap, table->addr, vals, i);
+-
+- if (ret) {
+- dev_err(imx214->dev, "write_table error: %d\n", ret);
+- return ret;
+- }
+-
+- table += i - 1;
+- }
+-
+- return 0;
+-}
+-
+ static int imx214_start_streaming(struct imx214 *imx214)
+ {
+ const struct v4l2_mbus_framefmt *fmt;
+@@ -774,7 +717,8 @@ static int imx214_start_streaming(struct imx214 *imx214)
+ const struct imx214_mode *mode;
+ int ret;
+
+- ret = imx214_write_table(imx214, mode_table_common);
++ ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
++ ARRAY_SIZE(mode_table_common), NULL);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sent common table %d\n", ret);
+ return ret;
+@@ -784,17 +728,24 @@ static int imx214_start_streaming(struct imx214 *imx214)
+ fmt = v4l2_subdev_state_get_format(state, 0);
+ mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes),
+ width, height, fmt->width, fmt->height);
+- ret = imx214_write_table(imx214, mode->reg_table);
++ ret = cci_multi_reg_write(imx214->regmap, mode->reg_table,
++ mode->num_of_regs, NULL);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sent mode table %d\n", ret);
+ return ret;
+ }
++
++ usleep_range(10000, 10500);
++
++ cci_write(imx214->regmap, CCI_REG8(0x0138), 0x01, NULL);
++
+ ret = __v4l2_ctrl_handler_setup(&imx214->ctrls);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sync v4l2 controls\n");
+ return ret;
+ }
+- ret = regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_STREAMING);
++ ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
++ IMX214_MODE_STREAMING, NULL);
+ if (ret < 0)
+ dev_err(imx214->dev, "could not sent start table %d\n", ret);
+
+@@ -805,7 +756,8 @@ static int imx214_stop_streaming(struct imx214 *imx214)
+ {
+ int ret;
+
+- ret = regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY);
++ ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
++ IMX214_MODE_STANDBY, NULL);
+ if (ret < 0)
+ dev_err(imx214->dev, "could not sent stop table %d\n", ret);
+
+@@ -906,12 +858,6 @@ static const struct v4l2_subdev_internal_ops imx214_internal_ops = {
+ .init_state = imx214_entity_init_state,
+ };
+
+-static const struct regmap_config sensor_regmap_config = {
+- .reg_bits = 16,
+- .val_bits = 8,
+- .cache_type = REGCACHE_MAPLE,
+-};
+-
+ static int imx214_get_regulators(struct device *dev, struct imx214 *imx214)
+ {
+ unsigned int i;
+@@ -995,10 +941,10 @@ static int imx214_probe(struct i2c_client *client)
+ return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio),
+ "failed to get enable gpio\n");
+
+- imx214->regmap = devm_regmap_init_i2c(client, &sensor_regmap_config);
++ imx214->regmap = devm_cci_regmap_init_i2c(client, 16);
+ if (IS_ERR(imx214->regmap))
+ return dev_err_probe(dev, PTR_ERR(imx214->regmap),
+- "regmap init failed\n");
++ "failed to initialize CCI\n");
+
+ v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops);
+ imx214->sd.internal_ops = &imx214_internal_ops;
+--
+2.39.5
+
--- /dev/null
+From 51f5207f5607b5c741c9227aaf11d13a169523ba Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:12 +0100
+Subject: media: i2c: imx214: Fix link frequency validation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit acc294519f1749041e1b8c74d46bbf6c57d8b061 ]
+
+The driver defines IMX214_DEFAULT_LINK_FREQ 480000000, and then
+IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10),
+which works out as 384MPix/s. (The 8 is 4 lanes and DDR.)
+
+Parsing the PLL registers with the defined 24MHz input. We're in single
+PLL mode, so MIPI frequency is directly linked to pixel rate. VTCK ends
+up being 1200MHz, and VTPXCK and OPPXCK both are 120MHz. Section 5.3
+"Frame rate calculation formula" says "Pixel rate
+[pixels/s] = VTPXCK [MHz] * 4", so 120 * 4 = 480MPix/s, which basically
+agrees with my number above.
+
+3.1.4. MIPI global timing setting says "Output bitrate = OPPXCK * reg
+0x113[7:0]", so 120MHz * 10, or 1200Mbit/s. That would be a link
+frequency of 600MHz due to DDR.
+That also matches to 480MPix/s * 10bpp / 4 lanes / 2 for DDR.
+
+Keep the previous link frequency for backward compatibility.
+
+Acked-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Fixes: 436190596241 ("media: imx214: Add imx214 camera sensor driver")
+Cc: stable@vger.kernel.org
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/imx214.c | 28 +++++++++++++++++++---------
+ 1 file changed, 19 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index fdc2dfb4ebcdd..bdf2396c2482b 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -27,7 +27,9 @@
+ #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106)
+
+ #define IMX214_DEFAULT_CLK_FREQ 24000000
+-#define IMX214_DEFAULT_LINK_FREQ 480000000
++#define IMX214_DEFAULT_LINK_FREQ 600000000
++/* Keep wrong link frequency for backward compatibility */
++#define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000
+ #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
+ #define IMX214_FPS 30
+ #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10
+@@ -965,18 +967,26 @@ static int imx214_parse_fwnode(struct device *dev)
+ goto done;
+ }
+
+- for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
++ if (bus_cfg.nr_of_link_frequencies != 1)
++ dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n");
++
++ for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
+ if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
+ break;
+-
+- if (i == bus_cfg.nr_of_link_frequencies) {
+- dev_err_probe(dev, -EINVAL,
+- "link-frequencies %d not supported, Please review your DT\n",
+- IMX214_DEFAULT_LINK_FREQ);
+- ret = -EINVAL;
+- goto done;
++ if (bus_cfg.link_frequencies[i] ==
++ IMX214_DEFAULT_LINK_FREQ_LEGACY) {
++ dev_warn(dev,
++ "link-frequencies %d not supported, please review your DT. Continuing anyway\n",
++ IMX214_DEFAULT_LINK_FREQ);
++ break;
++ }
+ }
+
++ if (i == bus_cfg.nr_of_link_frequencies)
++ ret = dev_err_probe(dev, -EINVAL,
++ "link-frequencies %d not supported, please review your DT\n",
++ IMX214_DEFAULT_LINK_FREQ);
++
+ done:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+ fwnode_handle_put(endpoint);
+--
+2.39.5
+
--- /dev/null
+From a14719b809a17dd9c28ce1ae79f0a1dc5511bcce Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:03 +0100
+Subject: media: i2c: imx214: Replace register addresses with macros
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit 341a133beb43f9009ebdde9eff276dfacbac114a ]
+
+Define macros for all the known registers used in the register arrays,
+and use them to replace the numerical addresses. This improves
+readability.
+
+Acked-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: acc294519f17 ("media: i2c: imx214: Fix link frequency validation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/imx214.c | 407 +++++++++++++++++++++----------------
+ 1 file changed, 236 insertions(+), 171 deletions(-)
+
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index 20d1ebebf13af..8bac5a1f1cb18 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -24,18 +24,141 @@
+ #define IMX214_MODE_STANDBY 0x00
+ #define IMX214_MODE_STREAMING 0x01
+
++#define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106)
++
+ #define IMX214_DEFAULT_CLK_FREQ 24000000
+ #define IMX214_DEFAULT_LINK_FREQ 480000000
+ #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
+ #define IMX214_FPS 30
+ #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10
+
++/* V-TIMING internal */
++#define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340)
++
+ /* Exposure control */
+ #define IMX214_REG_EXPOSURE CCI_REG16(0x0202)
+ #define IMX214_EXPOSURE_MIN 0
+ #define IMX214_EXPOSURE_MAX 3184
+ #define IMX214_EXPOSURE_STEP 1
+ #define IMX214_EXPOSURE_DEFAULT 3184
++#define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222)
++#define IMX214_REG_SHORT_EXPOSURE CCI_REG16(0x0224)
++
++/* Analog gain control */
++#define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204)
++#define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216)
++
++/* Digital gain control */
++#define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e)
++#define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210)
++#define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212)
++#define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214)
++
++#define IMX214_REG_ORIENTATION CCI_REG8(0x0101)
++
++#define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105)
++#define IMX214_CORR_FRAMES_TRANSMIT 0
++#define IMX214_CORR_FRAMES_MASK 1
++
++#define IMX214_REG_CSI_DATA_FORMAT CCI_REG16(0x0112)
++#define IMX214_CSI_DATA_FORMAT_RAW8 0x0808
++#define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A
++#define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06
++#define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08
++
++#define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
++#define IMX214_CSI_2_LANE_MODE 1
++#define IMX214_CSI_4_LANE_MODE 3
++
++#define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136)
++#define IMX214_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
++
++#define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138)
++
++#define IMX214_REG_HDR_MODE CCI_REG8(0x0220)
++#define IMX214_HDR_MODE_OFF 0
++#define IMX214_HDR_MODE_ON 1
++
++#define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221)
++#define IMX214_HDR_RES_REDU_THROUGH 0x11
++#define IMX214_HDR_RES_REDU_2_BINNING 0x22
++
++/* PLL settings */
++#define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301)
++#define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303)
++#define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
++#define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306)
++#define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309)
++#define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b)
++#define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
++#define IMX214_PLL_SINGLE 0
++#define IMX214_PLL_DUAL 1
++
++#define IMX214_REG_LINE_LENGTH_PCK CCI_REG16(0x0342)
++#define IMX214_REG_X_ADD_STA CCI_REG16(0x0344)
++#define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346)
++#define IMX214_REG_X_ADD_END CCI_REG16(0x0348)
++#define IMX214_REG_Y_ADD_END CCI_REG16(0x034a)
++#define IMX214_REG_X_OUTPUT_SIZE CCI_REG16(0x034c)
++#define IMX214_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e)
++#define IMX214_REG_X_EVEN_INC CCI_REG8(0x0381)
++#define IMX214_REG_X_ODD_INC CCI_REG8(0x0383)
++#define IMX214_REG_Y_EVEN_INC CCI_REG8(0x0385)
++#define IMX214_REG_Y_ODD_INC CCI_REG8(0x0387)
++
++#define IMX214_REG_SCALE_MODE CCI_REG8(0x0401)
++#define IMX214_SCALE_NONE 0
++#define IMX214_SCALE_HORIZONTAL 1
++#define IMX214_SCALE_FULL 2
++#define IMX214_REG_SCALE_M CCI_REG16(0x0404)
++
++#define IMX214_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408)
++#define IMX214_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a)
++#define IMX214_REG_DIG_CROP_WIDTH CCI_REG16(0x040c)
++#define IMX214_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e)
++
++#define IMX214_REG_REQ_LINK_BIT_RATE CCI_REG32(0x0820)
++#define IMX214_LINK_BIT_RATE_MBPS(n) ((n) << 16)
++
++/* Binning mode */
++#define IMX214_REG_BINNING_MODE CCI_REG8(0x0900)
++#define IMX214_BINNING_NONE 0
++#define IMX214_BINNING_ENABLE 1
++#define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901)
++#define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902)
++#define IMX214_BINNING_AVERAGE 0x00
++#define IMX214_BINNING_SUMMED 0x01
++#define IMX214_BINNING_BAYER 0x02
++
++#define IMX214_REG_SING_DEF_CORR_EN CCI_REG8(0x0b06)
++#define IMX214_SING_DEF_CORR_OFF 0
++#define IMX214_SING_DEF_CORR_ON 1
++
++/* AWB control */
++#define IMX214_REG_ABS_GAIN_GREENR CCI_REG16(0x0b8e)
++#define IMX214_REG_ABS_GAIN_RED CCI_REG16(0x0b90)
++#define IMX214_REG_ABS_GAIN_BLUE CCI_REG16(0x0b92)
++#define IMX214_REG_ABS_GAIN_GREENB CCI_REG16(0x0b94)
++
++#define IMX214_REG_RMSC_NR_MODE CCI_REG8(0x3001)
++#define IMX214_REG_STATS_OUT_EN CCI_REG8(0x3013)
++#define IMX214_STATS_OUT_OFF 0
++#define IMX214_STATS_OUT_ON 1
++
++/* Chroma noise reduction */
++#define IMX214_REG_NML_NR_EN CCI_REG8(0x30a2)
++#define IMX214_NML_NR_OFF 0
++#define IMX214_NML_NR_ON 1
++
++#define IMX214_REG_EBD_SIZE_V CCI_REG8(0x5041)
++#define IMX214_EBD_NO 0
++#define IMX214_EBD_4_LINE 4
++
++#define IMX214_REG_RG_STATS_LMT CCI_REG16(0x6d12)
++#define IMX214_RG_STATS_LMT_10_BIT 0x03FF
++#define IMX214_RG_STATS_LMT_14_BIT 0x3FFF
++
++#define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300)
+
+ /* IMX214 native and active pixel array size */
+ #define IMX214_NATIVE_WIDTH 4224U
+@@ -74,96 +197,70 @@ struct imx214 {
+
+ /*From imx214_mode_tbls.h*/
+ static const struct cci_reg_sequence mode_4096x2304[] = {
+- { CCI_REG8(0x0114), 0x03 },
+- { CCI_REG8(0x0220), 0x00 },
+- { CCI_REG8(0x0221), 0x11 },
+- { CCI_REG8(0x0222), 0x01 },
+- { CCI_REG8(0x0340), 0x0C },
+- { CCI_REG8(0x0341), 0x7A },
+- { CCI_REG8(0x0342), 0x13 },
+- { CCI_REG8(0x0343), 0x90 },
+- { CCI_REG8(0x0344), 0x00 },
+- { CCI_REG8(0x0345), 0x38 },
+- { CCI_REG8(0x0346), 0x01 },
+- { CCI_REG8(0x0347), 0x98 },
+- { CCI_REG8(0x0348), 0x10 },
+- { CCI_REG8(0x0349), 0x37 },
+- { CCI_REG8(0x034A), 0x0A },
+- { CCI_REG8(0x034B), 0x97 },
+- { CCI_REG8(0x0381), 0x01 },
+- { CCI_REG8(0x0383), 0x01 },
+- { CCI_REG8(0x0385), 0x01 },
+- { CCI_REG8(0x0387), 0x01 },
+- { CCI_REG8(0x0900), 0x00 },
+- { CCI_REG8(0x0901), 0x00 },
+- { CCI_REG8(0x0902), 0x00 },
++ { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE },
++ { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
++ { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
++ { IMX214_REG_EXPOSURE_RATIO, 1 },
++ { IMX214_REG_FRM_LENGTH_LINES, 3194 },
++ { IMX214_REG_LINE_LENGTH_PCK, 5008 },
++ { IMX214_REG_X_ADD_STA, 56 },
++ { IMX214_REG_Y_ADD_STA, 408 },
++ { IMX214_REG_X_ADD_END, 4151 },
++ { IMX214_REG_Y_ADD_END, 2711 },
++ { IMX214_REG_X_EVEN_INC, 1 },
++ { IMX214_REG_X_ODD_INC, 1 },
++ { IMX214_REG_Y_EVEN_INC, 1 },
++ { IMX214_REG_Y_ODD_INC, 1 },
++ { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
++ { IMX214_REG_BINNING_TYPE, 0 },
++ { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
+ { CCI_REG8(0x3000), 0x35 },
+ { CCI_REG8(0x3054), 0x01 },
+ { CCI_REG8(0x305C), 0x11 },
+
+- { CCI_REG8(0x0112), 0x0A },
+- { CCI_REG8(0x0113), 0x0A },
+- { CCI_REG8(0x034C), 0x10 },
+- { CCI_REG8(0x034D), 0x00 },
+- { CCI_REG8(0x034E), 0x09 },
+- { CCI_REG8(0x034F), 0x00 },
+- { CCI_REG8(0x0401), 0x00 },
+- { CCI_REG8(0x0404), 0x00 },
+- { CCI_REG8(0x0405), 0x10 },
+- { CCI_REG8(0x0408), 0x00 },
+- { CCI_REG8(0x0409), 0x00 },
+- { CCI_REG8(0x040A), 0x00 },
+- { CCI_REG8(0x040B), 0x00 },
+- { CCI_REG8(0x040C), 0x10 },
+- { CCI_REG8(0x040D), 0x00 },
+- { CCI_REG8(0x040E), 0x09 },
+- { CCI_REG8(0x040F), 0x00 },
+-
+- { CCI_REG8(0x0301), 0x05 },
+- { CCI_REG8(0x0303), 0x02 },
+- { CCI_REG8(0x0305), 0x03 },
+- { CCI_REG8(0x0306), 0x00 },
+- { CCI_REG8(0x0307), 0x96 },
+- { CCI_REG8(0x0309), 0x0A },
+- { CCI_REG8(0x030B), 0x01 },
+- { CCI_REG8(0x0310), 0x00 },
+-
+- { CCI_REG8(0x0820), 0x12 },
+- { CCI_REG8(0x0821), 0xC0 },
+- { CCI_REG8(0x0822), 0x00 },
+- { CCI_REG8(0x0823), 0x00 },
++ { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
++ { IMX214_REG_X_OUTPUT_SIZE, 4096 },
++ { IMX214_REG_Y_OUTPUT_SIZE, 2304 },
++ { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
++ { IMX214_REG_SCALE_M, 2 },
++ { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
++ { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
++ { IMX214_REG_DIG_CROP_WIDTH, 4096 },
++ { IMX214_REG_DIG_CROP_HEIGHT, 2304 },
++
++ { IMX214_REG_VTPXCK_DIV, 5 },
++ { IMX214_REG_VTSYCK_DIV, 2 },
++ { IMX214_REG_PREPLLCK_VT_DIV, 3 },
++ { IMX214_REG_PLL_VT_MPY, 150 },
++ { IMX214_REG_OPPXCK_DIV, 10 },
++ { IMX214_REG_OPSYCK_DIV, 1 },
++ { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
++
++ { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
+
+ { CCI_REG8(0x3A03), 0x09 },
+ { CCI_REG8(0x3A04), 0x50 },
+ { CCI_REG8(0x3A05), 0x01 },
+
+- { CCI_REG8(0x0B06), 0x01 },
+- { CCI_REG8(0x30A2), 0x00 },
++ { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
++ { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
+
+ { CCI_REG8(0x30B4), 0x00 },
+
+ { CCI_REG8(0x3A02), 0xFF },
+
+ { CCI_REG8(0x3011), 0x00 },
+- { CCI_REG8(0x3013), 0x01 },
+-
+- { CCI_REG8(0x0202), 0x0C },
+- { CCI_REG8(0x0203), 0x70 },
+- { CCI_REG8(0x0224), 0x01 },
+- { CCI_REG8(0x0225), 0xF4 },
+-
+- { CCI_REG8(0x0204), 0x00 },
+- { CCI_REG8(0x0205), 0x00 },
+- { CCI_REG8(0x020E), 0x01 },
+- { CCI_REG8(0x020F), 0x00 },
+- { CCI_REG8(0x0210), 0x01 },
+- { CCI_REG8(0x0211), 0x00 },
+- { CCI_REG8(0x0212), 0x01 },
+- { CCI_REG8(0x0213), 0x00 },
+- { CCI_REG8(0x0214), 0x01 },
+- { CCI_REG8(0x0215), 0x00 },
+- { CCI_REG8(0x0216), 0x00 },
+- { CCI_REG8(0x0217), 0x00 },
++ { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
++
++ { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT },
++ { IMX214_REG_SHORT_EXPOSURE, 500 },
++
++ { IMX214_REG_ANALOG_GAIN, 0 },
++ { IMX214_REG_DIG_GAIN_GREENR, 256 },
++ { IMX214_REG_DIG_GAIN_RED, 256 },
++ { IMX214_REG_DIG_GAIN_BLUE, 256 },
++ { IMX214_REG_DIG_GAIN_GREENB, 256 },
++ { IMX214_REG_SHORT_ANALOG_GAIN, 0 },
+
+ { CCI_REG8(0x4170), 0x00 },
+ { CCI_REG8(0x4171), 0x10 },
+@@ -174,96 +271,70 @@ static const struct cci_reg_sequence mode_4096x2304[] = {
+ };
+
+ static const struct cci_reg_sequence mode_1920x1080[] = {
+- { CCI_REG8(0x0114), 0x03 },
+- { CCI_REG8(0x0220), 0x00 },
+- { CCI_REG8(0x0221), 0x11 },
+- { CCI_REG8(0x0222), 0x01 },
+- { CCI_REG8(0x0340), 0x0C },
+- { CCI_REG8(0x0341), 0x7A },
+- { CCI_REG8(0x0342), 0x13 },
+- { CCI_REG8(0x0343), 0x90 },
+- { CCI_REG8(0x0344), 0x04 },
+- { CCI_REG8(0x0345), 0x78 },
+- { CCI_REG8(0x0346), 0x03 },
+- { CCI_REG8(0x0347), 0xFC },
+- { CCI_REG8(0x0348), 0x0B },
+- { CCI_REG8(0x0349), 0xF7 },
+- { CCI_REG8(0x034A), 0x08 },
+- { CCI_REG8(0x034B), 0x33 },
+- { CCI_REG8(0x0381), 0x01 },
+- { CCI_REG8(0x0383), 0x01 },
+- { CCI_REG8(0x0385), 0x01 },
+- { CCI_REG8(0x0387), 0x01 },
+- { CCI_REG8(0x0900), 0x00 },
+- { CCI_REG8(0x0901), 0x00 },
+- { CCI_REG8(0x0902), 0x00 },
++ { IMX214_REG_CSI_LANE_MODE, IMX214_CSI_4_LANE_MODE },
++ { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
++ { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
++ { IMX214_REG_EXPOSURE_RATIO, 1 },
++ { IMX214_REG_FRM_LENGTH_LINES, 3194 },
++ { IMX214_REG_LINE_LENGTH_PCK, 5008 },
++ { IMX214_REG_X_ADD_STA, 1144 },
++ { IMX214_REG_Y_ADD_STA, 1020 },
++ { IMX214_REG_X_ADD_END, 3063 },
++ { IMX214_REG_Y_ADD_END, 2099 },
++ { IMX214_REG_X_EVEN_INC, 1 },
++ { IMX214_REG_X_ODD_INC, 1 },
++ { IMX214_REG_Y_EVEN_INC, 1 },
++ { IMX214_REG_Y_ODD_INC, 1 },
++ { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
++ { IMX214_REG_BINNING_TYPE, 0 },
++ { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
+ { CCI_REG8(0x3000), 0x35 },
+ { CCI_REG8(0x3054), 0x01 },
+ { CCI_REG8(0x305C), 0x11 },
+
+- { CCI_REG8(0x0112), 0x0A },
+- { CCI_REG8(0x0113), 0x0A },
+- { CCI_REG8(0x034C), 0x07 },
+- { CCI_REG8(0x034D), 0x80 },
+- { CCI_REG8(0x034E), 0x04 },
+- { CCI_REG8(0x034F), 0x38 },
+- { CCI_REG8(0x0401), 0x00 },
+- { CCI_REG8(0x0404), 0x00 },
+- { CCI_REG8(0x0405), 0x10 },
+- { CCI_REG8(0x0408), 0x00 },
+- { CCI_REG8(0x0409), 0x00 },
+- { CCI_REG8(0x040A), 0x00 },
+- { CCI_REG8(0x040B), 0x00 },
+- { CCI_REG8(0x040C), 0x07 },
+- { CCI_REG8(0x040D), 0x80 },
+- { CCI_REG8(0x040E), 0x04 },
+- { CCI_REG8(0x040F), 0x38 },
+-
+- { CCI_REG8(0x0301), 0x05 },
+- { CCI_REG8(0x0303), 0x02 },
+- { CCI_REG8(0x0305), 0x03 },
+- { CCI_REG8(0x0306), 0x00 },
+- { CCI_REG8(0x0307), 0x96 },
+- { CCI_REG8(0x0309), 0x0A },
+- { CCI_REG8(0x030B), 0x01 },
+- { CCI_REG8(0x0310), 0x00 },
+-
+- { CCI_REG8(0x0820), 0x12 },
+- { CCI_REG8(0x0821), 0xC0 },
+- { CCI_REG8(0x0822), 0x00 },
+- { CCI_REG8(0x0823), 0x00 },
++ { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
++ { IMX214_REG_X_OUTPUT_SIZE, 1920 },
++ { IMX214_REG_Y_OUTPUT_SIZE, 1080 },
++ { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
++ { IMX214_REG_SCALE_M, 2 },
++ { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
++ { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
++ { IMX214_REG_DIG_CROP_WIDTH, 1920 },
++ { IMX214_REG_DIG_CROP_HEIGHT, 1080 },
++
++ { IMX214_REG_VTPXCK_DIV, 5 },
++ { IMX214_REG_VTSYCK_DIV, 2 },
++ { IMX214_REG_PREPLLCK_VT_DIV, 3 },
++ { IMX214_REG_PLL_VT_MPY, 150 },
++ { IMX214_REG_OPPXCK_DIV, 10 },
++ { IMX214_REG_OPSYCK_DIV, 1 },
++ { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
++
++ { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
+
+ { CCI_REG8(0x3A03), 0x04 },
+ { CCI_REG8(0x3A04), 0xF8 },
+ { CCI_REG8(0x3A05), 0x02 },
+
+- { CCI_REG8(0x0B06), 0x01 },
+- { CCI_REG8(0x30A2), 0x00 },
++ { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
++ { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
+
+ { CCI_REG8(0x30B4), 0x00 },
+
+ { CCI_REG8(0x3A02), 0xFF },
+
+ { CCI_REG8(0x3011), 0x00 },
+- { CCI_REG8(0x3013), 0x01 },
+-
+- { CCI_REG8(0x0202), 0x0C },
+- { CCI_REG8(0x0203), 0x70 },
+- { CCI_REG8(0x0224), 0x01 },
+- { CCI_REG8(0x0225), 0xF4 },
+-
+- { CCI_REG8(0x0204), 0x00 },
+- { CCI_REG8(0x0205), 0x00 },
+- { CCI_REG8(0x020E), 0x01 },
+- { CCI_REG8(0x020F), 0x00 },
+- { CCI_REG8(0x0210), 0x01 },
+- { CCI_REG8(0x0211), 0x00 },
+- { CCI_REG8(0x0212), 0x01 },
+- { CCI_REG8(0x0213), 0x00 },
+- { CCI_REG8(0x0214), 0x01 },
+- { CCI_REG8(0x0215), 0x00 },
+- { CCI_REG8(0x0216), 0x00 },
+- { CCI_REG8(0x0217), 0x00 },
++ { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
++
++ { IMX214_REG_EXPOSURE, IMX214_EXPOSURE_DEFAULT },
++ { IMX214_REG_SHORT_EXPOSURE, 500 },
++
++ { IMX214_REG_ANALOG_GAIN, 0 },
++ { IMX214_REG_DIG_GAIN_GREENR, 256 },
++ { IMX214_REG_DIG_GAIN_RED, 256 },
++ { IMX214_REG_DIG_GAIN_BLUE, 256 },
++ { IMX214_REG_DIG_GAIN_GREENB, 256 },
++ { IMX214_REG_SHORT_ANALOG_GAIN, 0 },
+
+ { CCI_REG8(0x4170), 0x00 },
+ { CCI_REG8(0x4171), 0x10 },
+@@ -277,20 +348,19 @@ static const struct cci_reg_sequence mode_table_common[] = {
+ /* software reset */
+
+ /* software standby settings */
+- { CCI_REG8(0x0100), 0x00 },
++ { IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY },
+
+ /* ATR setting */
+- { CCI_REG8(0x9300), 0x02 },
++ { IMX214_REG_ATR_FAST_MOVE, 2 },
+
+ /* external clock setting */
+- { CCI_REG8(0x0136), 0x18 },
+- { CCI_REG8(0x0137), 0x00 },
++ { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000) },
+
+ /* global setting */
+ /* basic config */
+- { CCI_REG8(0x0101), 0x00 },
+- { CCI_REG8(0x0105), 0x01 },
+- { CCI_REG8(0x0106), 0x01 },
++ { IMX214_REG_ORIENTATION, 0 },
++ { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK },
++ { IMX214_REG_FAST_STANDBY_CTRL, 1 },
+ { CCI_REG8(0x4550), 0x02 },
+ { CCI_REG8(0x4601), 0x00 },
+ { CCI_REG8(0x4642), 0x05 },
+@@ -335,18 +405,17 @@ static const struct cci_reg_sequence mode_table_common[] = {
+ { CCI_REG8(0x4A87), 0xFF },
+
+ /* embedded data */
+- { CCI_REG8(0x5041), 0x04 },
++ { IMX214_REG_EBD_SIZE_V, IMX214_EBD_4_LINE },
+ { CCI_REG8(0x583C), 0x04 },
+ { CCI_REG8(0x620E), 0x04 },
+ { CCI_REG8(0x6EB2), 0x01 },
+ { CCI_REG8(0x6EB3), 0x00 },
+- { CCI_REG8(0x9300), 0x02 },
++ { IMX214_REG_ATR_FAST_MOVE, 2 },
+
+ /* imagequality */
+ /* HDR setting */
+- { CCI_REG8(0x3001), 0x07 },
+- { CCI_REG8(0x6D12), 0x3F },
+- { CCI_REG8(0x6D13), 0xFF },
++ { IMX214_REG_RMSC_NR_MODE, 0x07 },
++ { IMX214_REG_RG_STATS_LMT, IMX214_RG_STATS_LMT_14_BIT },
+ { CCI_REG8(0x9344), 0x03 },
+ { CCI_REG8(0x9706), 0x10 },
+ { CCI_REG8(0x9707), 0x03 },
+@@ -374,14 +443,10 @@ static const struct cci_reg_sequence mode_table_common[] = {
+ { CCI_REG8(0x698B), 0x03 },
+
+ /* white balanace */
+- { CCI_REG8(0x0B8E), 0x01 },
+- { CCI_REG8(0x0B8F), 0x00 },
+- { CCI_REG8(0x0B90), 0x01 },
+- { CCI_REG8(0x0B91), 0x00 },
+- { CCI_REG8(0x0B92), 0x01 },
+- { CCI_REG8(0x0B93), 0x00 },
+- { CCI_REG8(0x0B94), 0x01 },
+- { CCI_REG8(0x0B95), 0x00 },
++ { IMX214_REG_ABS_GAIN_GREENR, 0x0100 },
++ { IMX214_REG_ABS_GAIN_RED, 0x0100 },
++ { IMX214_REG_ABS_GAIN_BLUE, 0x0100 },
++ { IMX214_REG_ABS_GAIN_GREENB, 0x0100 },
+
+ /* ATR setting */
+ { CCI_REG8(0x6E50), 0x00 },
+@@ -737,7 +802,7 @@ static int imx214_start_streaming(struct imx214 *imx214)
+
+ usleep_range(10000, 10500);
+
+- cci_write(imx214->regmap, CCI_REG8(0x0138), 0x01, NULL);
++ cci_write(imx214->regmap, IMX214_REG_TEMP_SENSOR_CONTROL, 0x01, NULL);
+
+ ret = __v4l2_ctrl_handler_setup(&imx214->ctrls);
+ if (ret < 0) {
+--
+2.39.5
+
--- /dev/null
+From 9c3f4a37fc50f40fedba72d24d9bb7116bfe47dd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:01 +0100
+Subject: media: i2c: imx214: Simplify with dev_err_probe()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit 5d6dc133e6e4053b4b92a15a2e1b99d54b3f8adb ]
+
+Error handling in probe() can be a bit simpler with dev_err_probe().
+
+Acked-by: Ricardo Ribalda <ribalda@chromium.org>
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: acc294519f17 ("media: i2c: imx214: Fix link frequency validation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/imx214.c | 54 +++++++++++++++++---------------------
+ 1 file changed, 24 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index af6a3859c3f13..db6cdc3b65e37 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -933,14 +933,12 @@ static int imx214_parse_fwnode(struct device *dev)
+ int ret;
+
+ endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
+- if (!endpoint) {
+- dev_err(dev, "endpoint node not found\n");
+- return -EINVAL;
+- }
++ if (!endpoint)
++ return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
+ if (ret) {
+- dev_err(dev, "parsing endpoint node failed\n");
++ dev_err_probe(dev, ret, "parsing endpoint node failed\n");
+ goto done;
+ }
+
+@@ -949,8 +947,9 @@ static int imx214_parse_fwnode(struct device *dev)
+ break;
+
+ if (i == bus_cfg.nr_of_link_frequencies) {
+- dev_err(dev, "link-frequencies %d not supported, Please review your DT\n",
+- IMX214_DEFAULT_LINK_FREQ);
++ dev_err_probe(dev, -EINVAL,
++ "link-frequencies %d not supported, Please review your DT\n",
++ IMX214_DEFAULT_LINK_FREQ);
+ ret = -EINVAL;
+ goto done;
+ }
+@@ -978,34 +977,28 @@ static int imx214_probe(struct i2c_client *client)
+ imx214->dev = dev;
+
+ imx214->xclk = devm_clk_get(dev, NULL);
+- if (IS_ERR(imx214->xclk)) {
+- dev_err(dev, "could not get xclk");
+- return PTR_ERR(imx214->xclk);
+- }
++ if (IS_ERR(imx214->xclk))
++ return dev_err_probe(dev, PTR_ERR(imx214->xclk),
++ "failed to get xclk\n");
+
+ ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ);
+- if (ret) {
+- dev_err(dev, "could not set xclk frequency\n");
+- return ret;
+- }
++ if (ret)
++ return dev_err_probe(dev, ret,
++ "failed to set xclk frequency\n");
+
+ ret = imx214_get_regulators(dev, imx214);
+- if (ret < 0) {
+- dev_err(dev, "cannot get regulators\n");
+- return ret;
+- }
++ if (ret < 0)
++ return dev_err_probe(dev, ret, "failed to get regulators\n");
+
+ imx214->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+- if (IS_ERR(imx214->enable_gpio)) {
+- dev_err(dev, "cannot get enable gpio\n");
+- return PTR_ERR(imx214->enable_gpio);
+- }
++ if (IS_ERR(imx214->enable_gpio))
++ return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio),
++ "failed to get enable gpio\n");
+
+ imx214->regmap = devm_regmap_init_i2c(client, &sensor_regmap_config);
+- if (IS_ERR(imx214->regmap)) {
+- dev_err(dev, "regmap init failed\n");
+- return PTR_ERR(imx214->regmap);
+- }
++ if (IS_ERR(imx214->regmap))
++ return dev_err_probe(dev, PTR_ERR(imx214->regmap),
++ "regmap init failed\n");
+
+ v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops);
+ imx214->sd.internal_ops = &imx214_internal_ops;
+@@ -1027,14 +1020,14 @@ static int imx214_probe(struct i2c_client *client)
+
+ ret = media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad);
+ if (ret < 0) {
+- dev_err(dev, "could not register media entity\n");
++ dev_err_probe(dev, ret, "failed to init entity pads\n");
+ goto free_ctrl;
+ }
+
+ imx214->sd.state_lock = imx214->ctrls.lock;
+ ret = v4l2_subdev_init_finalize(&imx214->sd);
+ if (ret < 0) {
+- dev_err(dev, "subdev init error: %d\n", ret);
++ dev_err_probe(dev, ret, "subdev init error\n");
+ goto free_entity;
+ }
+
+@@ -1043,7 +1036,8 @@ static int imx214_probe(struct i2c_client *client)
+
+ ret = v4l2_async_register_subdev_sensor(&imx214->sd);
+ if (ret < 0) {
+- dev_err(dev, "could not register v4l2 device\n");
++ dev_err_probe(dev, ret,
++ "failed to register sensor sub-device\n");
+ goto error_subdev_cleanup;
+ }
+
+--
+2.39.5
+
--- /dev/null
+From 24faabd7df7836cfc01007e32931179a39c3516a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 14:26:00 +0100
+Subject: media: i2c: imx214: Use subdev active state
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: André Apitzsch <git@apitzsch.eu>
+
+[ Upstream commit b6832ff659f55f86198bb8de40f278a20bda0920 ]
+
+Port the imx214 sensor driver to use the subdev active state.
+
+Move all the format configuration to the subdevice state and simplify
+the format handling, locking and initialization.
+
+While at it, simplify imx214_start_streaming() by removing unneeded goto
+statements and the corresponding error label.
+
+Signed-off-by: André Apitzsch <git@apitzsch.eu>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: acc294519f17 ("media: i2c: imx214: Fix link frequency validation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/imx214.c | 155 ++++++++++++-------------------------
+ 1 file changed, 50 insertions(+), 105 deletions(-)
+
+diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
+index 6a393e18267f4..af6a3859c3f13 100644
+--- a/drivers/media/i2c/imx214.c
++++ b/drivers/media/i2c/imx214.c
+@@ -59,8 +59,6 @@ struct imx214 {
+
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+- struct v4l2_mbus_framefmt fmt;
+- struct v4l2_rect crop;
+
+ struct v4l2_ctrl_handler ctrls;
+ struct v4l2_ctrl *pixel_rate;
+@@ -71,12 +69,6 @@ struct imx214 {
+ struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES];
+
+ struct gpio_desc *enable_gpio;
+-
+- /*
+- * Serialize control access, get/set format, get selection
+- * and start streaming.
+- */
+- struct mutex mutex;
+ };
+
+ struct reg_8 {
+@@ -490,6 +482,22 @@ static int __maybe_unused imx214_power_off(struct device *dev)
+ return 0;
+ }
+
++static void imx214_update_pad_format(struct imx214 *imx214,
++ const struct imx214_mode *mode,
++ struct v4l2_mbus_framefmt *fmt, u32 code)
++{
++ fmt->code = IMX214_MBUS_CODE;
++ fmt->width = mode->width;
++ fmt->height = mode->height;
++ fmt->field = V4L2_FIELD_NONE;
++ fmt->colorspace = V4L2_COLORSPACE_SRGB;
++ fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
++ fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
++ fmt->colorspace,
++ fmt->ycbcr_enc);
++ fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
++}
++
+ static int imx214_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+@@ -549,52 +557,6 @@ static const struct v4l2_subdev_core_ops imx214_core_ops = {
+ #endif
+ };
+
+-static struct v4l2_mbus_framefmt *
+-__imx214_get_pad_format(struct imx214 *imx214,
+- struct v4l2_subdev_state *sd_state,
+- unsigned int pad,
+- enum v4l2_subdev_format_whence which)
+-{
+- switch (which) {
+- case V4L2_SUBDEV_FORMAT_TRY:
+- return v4l2_subdev_state_get_format(sd_state, pad);
+- case V4L2_SUBDEV_FORMAT_ACTIVE:
+- return &imx214->fmt;
+- default:
+- return NULL;
+- }
+-}
+-
+-static int imx214_get_format(struct v4l2_subdev *sd,
+- struct v4l2_subdev_state *sd_state,
+- struct v4l2_subdev_format *format)
+-{
+- struct imx214 *imx214 = to_imx214(sd);
+-
+- mutex_lock(&imx214->mutex);
+- format->format = *__imx214_get_pad_format(imx214, sd_state,
+- format->pad,
+- format->which);
+- mutex_unlock(&imx214->mutex);
+-
+- return 0;
+-}
+-
+-static struct v4l2_rect *
+-__imx214_get_pad_crop(struct imx214 *imx214,
+- struct v4l2_subdev_state *sd_state,
+- unsigned int pad, enum v4l2_subdev_format_whence which)
+-{
+- switch (which) {
+- case V4L2_SUBDEV_FORMAT_TRY:
+- return v4l2_subdev_state_get_crop(sd_state, pad);
+- case V4L2_SUBDEV_FORMAT_ACTIVE:
+- return &imx214->crop;
+- default:
+- return NULL;
+- }
+-}
+-
+ static int imx214_set_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *format)
+@@ -604,34 +566,20 @@ static int imx214_set_format(struct v4l2_subdev *sd,
+ struct v4l2_rect *__crop;
+ const struct imx214_mode *mode;
+
+- mutex_lock(&imx214->mutex);
+-
+- __crop = __imx214_get_pad_crop(imx214, sd_state, format->pad,
+- format->which);
+-
+ mode = v4l2_find_nearest_size(imx214_modes,
+ ARRAY_SIZE(imx214_modes), width, height,
+ format->format.width,
+ format->format.height);
+
+- __crop->width = mode->width;
+- __crop->height = mode->height;
+-
+- __format = __imx214_get_pad_format(imx214, sd_state, format->pad,
+- format->which);
+- __format->width = __crop->width;
+- __format->height = __crop->height;
+- __format->code = IMX214_MBUS_CODE;
+- __format->field = V4L2_FIELD_NONE;
+- __format->colorspace = V4L2_COLORSPACE_SRGB;
+- __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
+- __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
+- __format->colorspace, __format->ycbcr_enc);
+- __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
++ imx214_update_pad_format(imx214, mode, &format->format,
++ format->format.code);
++ __format = v4l2_subdev_state_get_format(sd_state, 0);
+
+- format->format = *__format;
++ *__format = format->format;
+
+- mutex_unlock(&imx214->mutex);
++ __crop = v4l2_subdev_state_get_crop(sd_state, 0);
++ __crop->width = mode->width;
++ __crop->height = mode->height;
+
+ return 0;
+ }
+@@ -640,14 +588,9 @@ static int imx214_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+ {
+- struct imx214 *imx214 = to_imx214(sd);
+-
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+- mutex_lock(&imx214->mutex);
+- sel->r = *__imx214_get_pad_crop(imx214, sd_state, sel->pad,
+- sel->which);
+- mutex_unlock(&imx214->mutex);
++ sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
+ return 0;
+
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+@@ -826,40 +769,35 @@ static int imx214_write_table(struct imx214 *imx214,
+
+ static int imx214_start_streaming(struct imx214 *imx214)
+ {
++ const struct v4l2_mbus_framefmt *fmt;
++ struct v4l2_subdev_state *state;
+ const struct imx214_mode *mode;
+ int ret;
+
+- mutex_lock(&imx214->mutex);
+ ret = imx214_write_table(imx214, mode_table_common);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sent common table %d\n", ret);
+- goto error;
++ return ret;
+ }
+
+- mode = v4l2_find_nearest_size(imx214_modes,
+- ARRAY_SIZE(imx214_modes), width, height,
+- imx214->fmt.width, imx214->fmt.height);
++ state = v4l2_subdev_get_locked_active_state(&imx214->sd);
++ fmt = v4l2_subdev_state_get_format(state, 0);
++ mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes),
++ width, height, fmt->width, fmt->height);
+ ret = imx214_write_table(imx214, mode->reg_table);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sent mode table %d\n", ret);
+- goto error;
++ return ret;
+ }
+ ret = __v4l2_ctrl_handler_setup(&imx214->ctrls);
+ if (ret < 0) {
+ dev_err(imx214->dev, "could not sync v4l2 controls\n");
+- goto error;
++ return ret;
+ }
+ ret = regmap_write(imx214->regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_STREAMING);
+- if (ret < 0) {
++ if (ret < 0)
+ dev_err(imx214->dev, "could not sent start table %d\n", ret);
+- goto error;
+- }
+
+- mutex_unlock(&imx214->mutex);
+- return 0;
+-
+-error:
+- mutex_unlock(&imx214->mutex);
+ return ret;
+ }
+
+@@ -877,6 +815,7 @@ static int imx214_stop_streaming(struct imx214 *imx214)
+ static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
+ {
+ struct imx214 *imx214 = to_imx214(subdev);
++ struct v4l2_subdev_state *state;
+ int ret;
+
+ if (enable) {
+@@ -884,7 +823,9 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
+ if (ret < 0)
+ return ret;
+
++ state = v4l2_subdev_lock_and_get_active_state(subdev);
+ ret = imx214_start_streaming(imx214);
++ v4l2_subdev_unlock_state(state);
+ if (ret < 0)
+ goto err_rpm_put;
+ } else {
+@@ -948,7 +889,7 @@ static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = {
+ .enum_mbus_code = imx214_enum_mbus_code,
+ .enum_frame_size = imx214_enum_frame_size,
+ .enum_frame_interval = imx214_enum_frame_interval,
+- .get_fmt = imx214_get_format,
++ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = imx214_set_format,
+ .get_selection = imx214_get_selection,
+ .get_frame_interval = imx214_get_frame_interval,
+@@ -1079,9 +1020,6 @@ static int imx214_probe(struct i2c_client *client)
+ if (ret < 0)
+ goto error_power_off;
+
+- mutex_init(&imx214->mutex);
+- imx214->ctrls.lock = &imx214->mutex;
+-
+ imx214->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ imx214->pad.flags = MEDIA_PAD_FL_SOURCE;
+ imx214->sd.dev = &client->dev;
+@@ -1093,7 +1031,12 @@ static int imx214_probe(struct i2c_client *client)
+ goto free_ctrl;
+ }
+
+- imx214_entity_init_state(&imx214->sd, NULL);
++ imx214->sd.state_lock = imx214->ctrls.lock;
++ ret = v4l2_subdev_init_finalize(&imx214->sd);
++ if (ret < 0) {
++ dev_err(dev, "subdev init error: %d\n", ret);
++ goto free_entity;
++ }
+
+ pm_runtime_set_active(imx214->dev);
+ pm_runtime_enable(imx214->dev);
+@@ -1101,20 +1044,22 @@ static int imx214_probe(struct i2c_client *client)
+ ret = v4l2_async_register_subdev_sensor(&imx214->sd);
+ if (ret < 0) {
+ dev_err(dev, "could not register v4l2 device\n");
+- goto free_entity;
++ goto error_subdev_cleanup;
+ }
+
+ pm_runtime_idle(imx214->dev);
+
+ return 0;
+
+-free_entity:
++error_subdev_cleanup:
+ pm_runtime_disable(imx214->dev);
+ pm_runtime_set_suspended(&client->dev);
++ v4l2_subdev_cleanup(&imx214->sd);
++
++free_entity:
+ media_entity_cleanup(&imx214->sd.entity);
+
+ free_ctrl:
+- mutex_destroy(&imx214->mutex);
+ v4l2_ctrl_handler_free(&imx214->ctrls);
+
+ error_power_off:
+@@ -1129,9 +1074,9 @@ static void imx214_remove(struct i2c_client *client)
+ struct imx214 *imx214 = to_imx214(sd);
+
+ v4l2_async_unregister_subdev(&imx214->sd);
++ v4l2_subdev_cleanup(sd);
+ media_entity_cleanup(&imx214->sd.entity);
+ v4l2_ctrl_handler_free(&imx214->ctrls);
+- mutex_destroy(&imx214->mutex);
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev)) {
+ imx214_power_off(imx214->dev);
+--
+2.39.5
+
--- /dev/null
+From 2e18b0699d0d7b7ca753fa44759d0959ff26be75 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 15:41:28 +0100
+Subject: media: ov08x40: Add missing ov08x40_identify_module() call on
+ stream-start
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit ebf185efadb71bd5344877be683895b6b18d7edf ]
+
+The driver might skip the ov08x40_identify_module() on probe() based on
+the acpi_dev_state_d0() check done in probe().
+
+If the ov08x40_identify_module() call is skipped on probe() it should
+be done on the first stream start. Add the missing call.
+
+Note ov08x40_identify_module() will only do something on its first call,
+subsequent calls are no-ops.
+
+Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Fixes: b1a42fde6e07 ("media: ov08x40: Avoid sensor probing in D0 state")
+Cc: stable@vger.kernel.org
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/ov08x40.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c
+index 8b9c70dd70b88..1fe8e9b584f80 100644
+--- a/drivers/media/i2c/ov08x40.c
++++ b/drivers/media/i2c/ov08x40.c
+@@ -1908,6 +1908,10 @@ static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
+ if (ret < 0)
+ goto err_unlock;
+
++ ret = ov08x40_identify_module(ov08x);
++ if (ret)
++ goto err_rpm_put;
++
+ /*
+ * Apply default & customized values
+ * and then start streaming.
+--
+2.39.5
+
--- /dev/null
+From c1bafbffbdfa4333b1782e33891b0f6482a973ea Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 15:41:25 +0100
+Subject: media: ov08x40: Move ov08x40_identify_module() function up
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+[ Upstream commit 7a39639e448f070cbe37317ac922886b6080ff43 ]
+
+Move the ov08x40_identify_module() function to above ov08x40_set_stream()
+this is a preparation patch for adding a missing ov08x40_identify_module()
+call to ov08x40_set_stream().
+
+No functional changes, just moving code around.
+
+Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
+Stable-dep-of: ebf185efadb7 ("media: ov08x40: Add missing ov08x40_identify_module() call on stream-start")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/media/i2c/ov08x40.c | 52 ++++++++++++++++++-------------------
+ 1 file changed, 26 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c
+index 67b86dabc67eb..8b9c70dd70b88 100644
+--- a/drivers/media/i2c/ov08x40.c
++++ b/drivers/media/i2c/ov08x40.c
+@@ -1869,6 +1869,32 @@ static int ov08x40_stop_streaming(struct ov08x40 *ov08x)
+ OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY);
+ }
+
++/* Verify chip ID */
++static int ov08x40_identify_module(struct ov08x40 *ov08x)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
++ int ret;
++ u32 val;
++
++ if (ov08x->identified)
++ return 0;
++
++ ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID,
++ OV08X40_REG_VALUE_24BIT, &val);
++ if (ret)
++ return ret;
++
++ if (val != OV08X40_CHIP_ID) {
++ dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
++ OV08X40_CHIP_ID, val);
++ return -ENXIO;
++ }
++
++ ov08x->identified = true;
++
++ return 0;
++}
++
+ static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
+ {
+ struct ov08x40 *ov08x = to_ov08x40(sd);
+@@ -1906,32 +1932,6 @@ static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
+ return ret;
+ }
+
+-/* Verify chip ID */
+-static int ov08x40_identify_module(struct ov08x40 *ov08x)
+-{
+- struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
+- int ret;
+- u32 val;
+-
+- if (ov08x->identified)
+- return 0;
+-
+- ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID,
+- OV08X40_REG_VALUE_24BIT, &val);
+- if (ret)
+- return ret;
+-
+- if (val != OV08X40_CHIP_ID) {
+- dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
+- OV08X40_CHIP_ID, val);
+- return -ENXIO;
+- }
+-
+- ov08x->identified = true;
+-
+- return 0;
+-}
+-
+ static const struct v4l2_subdev_video_ops ov08x40_video_ops = {
+ .s_stream = ov08x40_set_stream,
+ };
+--
+2.39.5
+
--- /dev/null
+From aa4e73deaec86f96feacf4e793b63cb692c8166e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 18 Mar 2025 16:39:39 +0800
+Subject: mm/vmscan: don't try to reclaim hwpoison folio
+
+From: Jinjiang Tu <tujinjiang@huawei.com>
+
+[ Upstream commit 1b0449544c6482179ac84530b61fc192a6527bfd ]
+
+Syzkaller reports a bug as follows:
+
+Injecting memory failure for pfn 0x18b00e at process virtual address 0x20ffd000
+Memory failure: 0x18b00e: dirty swapcache page still referenced by 2 users
+Memory failure: 0x18b00e: recovery action for dirty swapcache page: Failed
+page: refcount:2 mapcount:0 mapping:0000000000000000 index:0x20ffd pfn:0x18b00e
+memcg:ffff0000dd6d9000
+anon flags: 0x5ffffe00482011(locked|dirty|arch_1|swapbacked|hwpoison|node=0|zone=2|lastcpupid=0xfffff)
+raw: 005ffffe00482011 dead000000000100 dead000000000122 ffff0000e232a7c9
+raw: 0000000000020ffd 0000000000000000 00000002ffffffff ffff0000dd6d9000
+page dumped because: VM_BUG_ON_FOLIO(!folio_test_uptodate(folio))
+------------[ cut here ]------------
+kernel BUG at mm/swap_state.c:184!
+Internal error: Oops - BUG: 00000000f2000800 [#1] SMP
+Modules linked in:
+CPU: 0 PID: 60 Comm: kswapd0 Not tainted 6.6.0-gcb097e7de84e #3
+Hardware name: linux,dummy-virt (DT)
+pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
+pc : add_to_swap+0xbc/0x158
+lr : add_to_swap+0xbc/0x158
+sp : ffff800087f37340
+x29: ffff800087f37340 x28: fffffc00052c0380 x27: ffff800087f37780
+x26: ffff800087f37490 x25: ffff800087f37c78 x24: ffff800087f377a0
+x23: ffff800087f37c50 x22: 0000000000000000 x21: fffffc00052c03b4
+x20: 0000000000000000 x19: fffffc00052c0380 x18: 0000000000000000
+x17: 296f696c6f662865 x16: 7461646f7470755f x15: 747365745f6f696c
+x14: 6f6621284f494c4f x13: 0000000000000001 x12: ffff600036d8b97b
+x11: 1fffe00036d8b97a x10: ffff600036d8b97a x9 : dfff800000000000
+x8 : 00009fffc9274686 x7 : ffff0001b6c5cbd3 x6 : 0000000000000001
+x5 : ffff0000c25896c0 x4 : 0000000000000000 x3 : 0000000000000000
+x2 : 0000000000000000 x1 : ffff0000c25896c0 x0 : 0000000000000000
+Call trace:
+ add_to_swap+0xbc/0x158
+ shrink_folio_list+0x12ac/0x2648
+ shrink_inactive_list+0x318/0x948
+ shrink_lruvec+0x450/0x720
+ shrink_node_memcgs+0x280/0x4a8
+ shrink_node+0x128/0x978
+ balance_pgdat+0x4f0/0xb20
+ kswapd+0x228/0x438
+ kthread+0x214/0x230
+ ret_from_fork+0x10/0x20
+
+I can reproduce this issue with the following steps:
+
+1) When a dirty swapcache page is isolated by reclaim process and the
+ page isn't locked, inject memory failure for the page.
+ me_swapcache_dirty() clears uptodate flag and tries to delete from lru,
+ but fails. Reclaim process will put the hwpoisoned page back to lru.
+
+2) The process that maps the hwpoisoned page exits, the page is deleted
+ the page will never be freed and will be in the lru forever.
+
+3) If we trigger a reclaim again and tries to reclaim the page,
+ add_to_swap() will trigger VM_BUG_ON_FOLIO due to the uptodate flag is
+ cleared.
+
+To fix it, skip the hwpoisoned page in shrink_folio_list(). Besides, the
+hwpoison folio may not be unmapped by hwpoison_user_mappings() yet, unmap
+it in shrink_folio_list(), otherwise the folio will fail to be unmaped by
+hwpoison_user_mappings() since the folio isn't in lru list.
+
+Link: https://lkml.kernel.org/r/20250318083939.987651-3-tujinjiang@huawei.com
+Signed-off-by: Jinjiang Tu <tujinjiang@huawei.com>
+Acked-by: Miaohe Lin <linmiaohe@huawei.com>
+Cc: David Hildenbrand <david@redhat.com>
+Cc: Kefeng Wang <wangkefeng.wang@huawei.com>
+Cc: Nanyong Sun <sunnanyong@huawei.com>
+Cc: Naoya Horiguchi <nao.horiguchi@gmail.com>
+Cc: <stable@vger,kernel.org>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ mm/vmscan.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/mm/vmscan.c b/mm/vmscan.c
+index 39b3c7f35ea85..0eb5d510d4f6b 100644
+--- a/mm/vmscan.c
++++ b/mm/vmscan.c
+@@ -1079,6 +1079,13 @@ static unsigned int shrink_folio_list(struct list_head *folio_list,
+ if (!folio_trylock(folio))
+ goto keep;
+
++ if (folio_contain_hwpoisoned_page(folio)) {
++ unmap_poisoned_folio(folio, folio_pfn(folio), false);
++ folio_unlock(folio);
++ folio_put(folio);
++ continue;
++ }
++
+ VM_BUG_ON_FOLIO(folio_test_active(folio), folio);
+
+ nr_pages = folio_nr_pages(folio);
+--
+2.39.5
+
--- /dev/null
+From 3dc954f2441a3fc54eb8e7b42b0e768bd40701b5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 17 Jan 2025 14:18:51 +0000
+Subject: mmc: sdhci-msm: fix dev reference leaked through of_qcom_ice_get
+
+From: Tudor Ambarus <tudor.ambarus@linaro.org>
+
+[ Upstream commit cbef7442fba510b7eb229dcc9f39d3dde4a159a4 ]
+
+The driver leaks the device reference taken with
+of_find_device_by_node(). Fix the leak by using devm_of_qcom_ice_get().
+
+Fixes: c7eed31e235c ("mmc: sdhci-msm: Switch to the new ICE API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20250117-qcom-ice-fix-dev-leak-v2-2-1ffa5b6884cb@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/sdhci-msm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
+index 945d08531de37..82808cc373f68 100644
+--- a/drivers/mmc/host/sdhci-msm.c
++++ b/drivers/mmc/host/sdhci-msm.c
+@@ -1866,7 +1866,7 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
+ if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
+ return 0;
+
+- ice = of_qcom_ice_get(dev);
++ ice = devm_of_qcom_ice_get(dev);
+ if (ice == ERR_PTR(-EOPNOTSUPP)) {
+ dev_warn(dev, "Disabling inline encryption support\n");
+ ice = NULL;
+--
+2.39.5
+
--- /dev/null
+From 266e772486c02db2003578a0a61bb15d86709fae Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Mar 2025 18:32:44 +0100
+Subject: net: dsa: mv88e6xxx: fix VTU methods for 6320 family
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Marek Behún <kabel@kernel.org>
+
+[ Upstream commit f9a457722cf5e3534be5ffab549d6b49737fca72 ]
+
+The VTU registers of the 6320 family use the 6352 semantics, not 6185.
+Fix it.
+
+Fixes: b8fee9571063 ("net: dsa: mv88e6xxx: add VLAN Get Next support")
+Signed-off-by: Marek Behún <kabel@kernel.org>
+Cc: <stable@vger.kernel.org> # 5.15.x
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/20250317173250.28780-2-kabel@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
+index df1df60154121..28967a338aa94 100644
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -5210,8 +5210,8 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
+ .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
+ .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
+ .reset = mv88e6352_g1_reset,
+- .vtu_getnext = mv88e6185_g1_vtu_getnext,
+- .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
++ .vtu_getnext = mv88e6352_g1_vtu_getnext,
++ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+@@ -5259,8 +5259,8 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
+ .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
+ .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
+ .reset = mv88e6352_g1_reset,
+- .vtu_getnext = mv88e6185_g1_vtu_getnext,
+- .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
++ .vtu_getnext = mv88e6352_g1_vtu_getnext,
++ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .gpio_ops = &mv88e6352_gpio_ops,
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+--
+2.39.5
+
--- /dev/null
+From 034122abb09659b45d6011582638ccaf5247019e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 17 Nov 2024 17:48:43 -0600
+Subject: net/niu: Niu requires MSIX ENTRY_DATA fields touch before entry reads
+
+From: Jonathan Currier <dullfire@yahoo.com>
+
+[ Upstream commit fbb429ddff5c8e479edcc7dde5a542c9295944e6 ]
+
+Fix niu_try_msix() to not cause a fatal trap on sparc systems.
+
+Set PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST on the struct pci_dev to
+work around a bug in the hardware or firmware.
+
+For each vector entry in the msix table, niu chips will cause a fatal
+trap if any registers in that entry are read before that entries'
+ENTRY_DATA register is written to. Testing indicates writes to other
+registers are not sufficient to prevent the fatal trap, however the value
+does not appear to matter. This only needs to happen once after power up,
+so simply rebooting into a kernel lacking this fix will NOT cause the
+trap.
+
+NON-RESUMABLE ERROR: Reporting on cpu 64
+NON-RESUMABLE ERROR: TPC [0x00000000005f6900] <msix_prepare_msi_desc+0x90/0xa0>
+NON-RESUMABLE ERROR: RAW [4010000000000016:00000e37f93e32ff:0000000202000080:ffffffffffffffff
+NON-RESUMABLE ERROR: 0000000800000000:0000000000000000:0000000000000000:0000000000000000]
+NON-RESUMABLE ERROR: handle [0x4010000000000016] stick [0x00000e37f93e32ff]
+NON-RESUMABLE ERROR: type [precise nonresumable]
+NON-RESUMABLE ERROR: attrs [0x02000080] < ASI sp-faulted priv >
+NON-RESUMABLE ERROR: raddr [0xffffffffffffffff]
+NON-RESUMABLE ERROR: insn effective address [0x000000c50020000c]
+NON-RESUMABLE ERROR: size [0x8]
+NON-RESUMABLE ERROR: asi [0x00]
+CPU: 64 UID: 0 PID: 745 Comm: kworker/64:1 Not tainted 6.11.5 #63
+Workqueue: events work_for_cpu_fn
+TSTATE: 0000000011001602 TPC: 00000000005f6900 TNPC: 00000000005f6904 Y: 00000000 Not tainted
+TPC: <msix_prepare_msi_desc+0x90/0xa0>
+g0: 00000000000002e9 g1: 000000000000000c g2: 000000c50020000c g3: 0000000000000100
+g4: ffff8000470307c0 g5: ffff800fec5be000 g6: ffff800047a08000 g7: 0000000000000000
+o0: ffff800014feb000 o1: ffff800047a0b620 o2: 0000000000000011 o3: ffff800047a0b620
+o4: 0000000000000080 o5: 0000000000000011 sp: ffff800047a0ad51 ret_pc: 00000000005f7128
+RPC: <__pci_enable_msix_range+0x3cc/0x460>
+l0: 000000000000000d l1: 000000000000c01f l2: ffff800014feb0a8 l3: 0000000000000020
+l4: 000000000000c000 l5: 0000000000000001 l6: 0000000020000000 l7: ffff800047a0b734
+i0: ffff800014feb000 i1: ffff800047a0b730 i2: 0000000000000001 i3: 000000000000000d
+i4: 0000000000000000 i5: 0000000000000000 i6: ffff800047a0ae81 i7: 00000000101888b0
+I7: <niu_try_msix.constprop.0+0xc0/0x130 [niu]>
+Call Trace:
+[<00000000101888b0>] niu_try_msix.constprop.0+0xc0/0x130 [niu]
+[<000000001018f840>] niu_get_invariants+0x183c/0x207c [niu]
+[<00000000101902fc>] niu_pci_init_one+0x27c/0x2fc [niu]
+[<00000000005ef3e4>] local_pci_probe+0x28/0x74
+[<0000000000469240>] work_for_cpu_fn+0x8/0x1c
+[<000000000046b008>] process_scheduled_works+0x144/0x210
+[<000000000046b518>] worker_thread+0x13c/0x1c0
+[<00000000004710e0>] kthread+0xb8/0xc8
+[<00000000004060c8>] ret_from_fork+0x1c/0x2c
+[<0000000000000000>] 0x0
+Kernel panic - not syncing: Non-resumable error.
+
+Fixes: 7d5ec3d36123 ("PCI/MSI: Mask all unused MSI-X entries")
+Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/all/20241117234843.19236-3-dullfire@yahoo.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/sun/niu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/sun/niu.c b/drivers/net/ethernet/sun/niu.c
+index 41a27ae58cedf..f5449b73b9a76 100644
+--- a/drivers/net/ethernet/sun/niu.c
++++ b/drivers/net/ethernet/sun/niu.c
+@@ -9058,6 +9058,8 @@ static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
+ msi_vec[i].entry = i;
+ }
+
++ pdev->dev_flags |= PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST;
++
+ num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
+ if (num_irqs < 0) {
+ np->flags &= ~NIU_FLAGS_MSIX;
+--
+2.39.5
+
--- /dev/null
+From e2a1e5c929bb3ed1e8330f8f03bdca664273d282 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Feb 2025 17:01:55 -0600
+Subject: of: resolver: Fix device node refcount leakage in
+ of_resolve_phandles()
+
+From: Zijun Hu <quic_zijuhu@quicinc.com>
+
+[ Upstream commit a46a0805635d07de50c2ac71588345323c13b2f9 ]
+
+In of_resolve_phandles(), refcount of device node @local_fixups will be
+increased if the for_each_child_of_node() exits early, but nowhere to
+decrease the refcount, so cause refcount leakage for the node.
+
+Fix by using __free() on @local_fixups.
+
+Fixes: da56d04c806a ("of/resolver: Switch to new local fixups format.")
+Cc: stable@vger.kernel.org
+Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com>
+Link: https://lore.kernel.org/r/20250209-of_irq_fix-v2-9-93e3a2659aa7@quicinc.com
+[robh: Use __free() instead]
+Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/of/resolver.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
+index fce8bdac45f3e..7d935908b5431 100644
+--- a/drivers/of/resolver.c
++++ b/drivers/of/resolver.c
+@@ -249,8 +249,9 @@ static int adjust_local_phandle_references(struct device_node *local_fixups,
+ */
+ int of_resolve_phandles(struct device_node *overlay)
+ {
+- struct device_node *child, *local_fixups, *refnode;
++ struct device_node *child, *refnode;
+ struct device_node *overlay_fixups;
++ struct device_node __free(device_node) *local_fixups = NULL;
+ struct property *prop;
+ const char *refpath;
+ phandle phandle, phandle_delta;
+--
+2.39.5
+
--- /dev/null
+From 23bf402ab8cfa06727ad19eb7505437d21918de1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 9 Feb 2025 20:59:02 +0800
+Subject: of: resolver: Simplify of_resolve_phandles() using __free()
+
+From: Rob Herring (Arm) <robh@kernel.org>
+
+[ Upstream commit 5275e8b5293f65cc82a5ee5eab02dd573b911d6e ]
+
+Use the __free() cleanup to simplify of_resolve_phandles() and remove
+all the goto's.
+
+Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+Stable-dep-of: a46a0805635d ("of: resolver: Fix device node refcount leakage in of_resolve_phandles()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/of/resolver.c | 34 +++++++++++-----------------------
+ 1 file changed, 11 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
+index 5cf96776dd7d3..fce8bdac45f3e 100644
+--- a/drivers/of/resolver.c
++++ b/drivers/of/resolver.c
+@@ -250,24 +250,20 @@ static int adjust_local_phandle_references(struct device_node *local_fixups,
+ int of_resolve_phandles(struct device_node *overlay)
+ {
+ struct device_node *child, *local_fixups, *refnode;
+- struct device_node *tree_symbols, *overlay_fixups;
++ struct device_node *overlay_fixups;
+ struct property *prop;
+ const char *refpath;
+ phandle phandle, phandle_delta;
+ int err;
+
+- tree_symbols = NULL;
+-
+ if (!overlay) {
+ pr_err("null overlay\n");
+- err = -EINVAL;
+- goto out;
++ return -EINVAL;
+ }
+
+ if (!of_node_check_flag(overlay, OF_DETACHED)) {
+ pr_err("overlay not detached\n");
+- err = -EINVAL;
+- goto out;
++ return -EINVAL;
+ }
+
+ phandle_delta = live_tree_max_phandle() + 1;
+@@ -279,7 +275,7 @@ int of_resolve_phandles(struct device_node *overlay)
+
+ err = adjust_local_phandle_references(local_fixups, overlay, phandle_delta);
+ if (err)
+- goto out;
++ return err;
+
+ overlay_fixups = NULL;
+
+@@ -288,16 +284,13 @@ int of_resolve_phandles(struct device_node *overlay)
+ overlay_fixups = child;
+ }
+
+- if (!overlay_fixups) {
+- err = 0;
+- goto out;
+- }
++ if (!overlay_fixups)
++ return 0;
+
+- tree_symbols = of_find_node_by_path("/__symbols__");
++ struct device_node __free(device_node) *tree_symbols = of_find_node_by_path("/__symbols__");
+ if (!tree_symbols) {
+ pr_err("no symbols in root of device tree.\n");
+- err = -EINVAL;
+- goto out;
++ return -EINVAL;
+ }
+
+ for_each_property_of_node(overlay_fixups, prop) {
+@@ -311,14 +304,12 @@ int of_resolve_phandles(struct device_node *overlay)
+ if (err) {
+ pr_err("node label '%s' not found in live devicetree symbols table\n",
+ prop->name);
+- goto out;
++ return err;
+ }
+
+ refnode = of_find_node_by_path(refpath);
+- if (!refnode) {
+- err = -ENOENT;
+- goto out;
+- }
++ if (!refnode)
++ return -ENOENT;
+
+ phandle = refnode->phandle;
+ of_node_put(refnode);
+@@ -328,11 +319,8 @@ int of_resolve_phandles(struct device_node *overlay)
+ break;
+ }
+
+-out:
+ if (err)
+ pr_err("overlay phandle fixup failed: %d\n", err);
+- of_node_put(tree_symbols);
+-
+ return err;
+ }
+ EXPORT_SYMBOL_GPL(of_resolve_phandles);
+--
+2.39.5
+
--- /dev/null
+From 4437b8b5d0ed5c9488d5776e908f656c72dadf8a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 17 Nov 2024 17:48:42 -0600
+Subject: PCI/MSI: Add an option to write MSIX ENTRY_DATA before any reads
+
+From: Jonathan Currier <dullfire@yahoo.com>
+
+[ Upstream commit cf761e3dacc6ad5f65a4886d00da1f9681e6805a ]
+
+Commit 7d5ec3d36123 ("PCI/MSI: Mask all unused MSI-X entries") introduced a
+readl() from ENTRY_VECTOR_CTRL before the writel() to ENTRY_DATA.
+
+This is correct, however some hardware, like the Sun Neptune chips, the NIU
+module, will cause an error and/or fatal trap if any MSIX table entry is
+read before the corresponding ENTRY_DATA field is written to.
+
+Add an optional early writel() in msix_prepare_msi_desc().
+
+Fixes: 7d5ec3d36123 ("PCI/MSI: Mask all unused MSI-X entries")
+Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/all/20241117234843.19236-2-dullfire@yahoo.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/msi/msi.c | 3 +++
+ include/linux/pci.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
+index 6569ba3577fe6..8b88487886184 100644
+--- a/drivers/pci/msi/msi.c
++++ b/drivers/pci/msi/msi.c
+@@ -615,6 +615,9 @@ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc)
+ void __iomem *addr = pci_msix_desc_addr(desc);
+
+ desc->pci.msi_attrib.can_mask = 1;
++ /* Workaround for SUN NIU insanity, which requires write before read */
++ if (dev->dev_flags & PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST)
++ writel(0, addr + PCI_MSIX_ENTRY_DATA);
+ desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
+ }
+ }
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 74114acbb07fb..ade889ded4e1e 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -245,6 +245,8 @@ enum pci_dev_flags {
+ PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
+ /* Device does honor MSI masking despite saying otherwise */
+ PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
++ /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
++ PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
+ };
+
+ enum pci_irq_reroute_variant {
+--
+2.39.5
+
--- /dev/null
+From 611b092c92f6134fc45aaf71a5ef5501f8930e40 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Feb 2025 10:20:57 +0100
+Subject: PCI/MSI: Convert pci_msi_ignore_mask to per MSI domain flag
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Roger Pau Monne <roger.pau@citrix.com>
+
+[ Upstream commit c3164d2e0d181027da8fc94f8179d8607c3d440f ]
+
+Setting pci_msi_ignore_mask inhibits the toggling of the mask bit for both
+MSI and MSI-X entries globally, regardless of the IRQ chip they are using.
+Only Xen sets the pci_msi_ignore_mask when routing physical interrupts over
+event channels, to prevent PCI code from attempting to toggle the maskbit,
+as it's Xen that controls the bit.
+
+However, the pci_msi_ignore_mask being global will affect devices that use
+MSI interrupts but are not routing those interrupts over event channels
+(not using the Xen pIRQ chip). One example is devices behind a VMD PCI
+bridge. In that scenario the VMD bridge configures MSI(-X) using the
+normal IRQ chip (the pIRQ one in the Xen case), and devices behind the
+bridge configure the MSI entries using indexes into the VMD bridge MSI
+table. The VMD bridge then demultiplexes such interrupts and delivers to
+the destination device(s). Having pci_msi_ignore_mask set in that scenario
+prevents (un)masking of MSI entries for devices behind the VMD bridge.
+
+Move the signaling of no entry masking into the MSI domain flags, as that
+allows setting it on a per-domain basis. Set it for the Xen MSI domain
+that uses the pIRQ chip, while leaving it unset for the rest of the
+cases.
+
+Remove pci_msi_ignore_mask at once, since it was only used by Xen code, and
+with Xen dropping usage the variable is unneeded.
+
+This fixes using devices behind a VMD bridge on Xen PV hardware domains.
+
+Albeit Devices behind a VMD bridge are not known to Xen, that doesn't mean
+Linux cannot use them. By inhibiting the usage of
+VMD_FEAT_CAN_BYPASS_MSI_REMAP and the removal of the pci_msi_ignore_mask
+bodge devices behind a VMD bridge do work fine when use from a Linux Xen
+hardware domain. That's the whole point of the series.
+
+Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
+Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Juergen Gross <jgross@suse.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Message-ID: <20250219092059.90850-4-roger.pau@citrix.com>
+Signed-off-by: Juergen Gross <jgross@suse.com>
+Stable-dep-of: cf761e3dacc6 ("PCI/MSI: Add an option to write MSIX ENTRY_DATA before any reads")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/pci/xen.c | 8 ++------
+ drivers/pci/msi/msi.c | 37 +++++++++++++++++++++----------------
+ include/linux/msi.h | 3 ++-
+ kernel/irq/msi.c | 2 +-
+ 4 files changed, 26 insertions(+), 24 deletions(-)
+
+diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
+index 0f2fe524f60dc..b8755cde24199 100644
+--- a/arch/x86/pci/xen.c
++++ b/arch/x86/pci/xen.c
+@@ -436,7 +436,8 @@ static struct msi_domain_ops xen_pci_msi_domain_ops = {
+ };
+
+ static struct msi_domain_info xen_pci_msi_domain_info = {
+- .flags = MSI_FLAG_PCI_MSIX | MSI_FLAG_FREE_MSI_DESCS | MSI_FLAG_DEV_SYSFS,
++ .flags = MSI_FLAG_PCI_MSIX | MSI_FLAG_FREE_MSI_DESCS |
++ MSI_FLAG_DEV_SYSFS | MSI_FLAG_NO_MASK,
+ .ops = &xen_pci_msi_domain_ops,
+ };
+
+@@ -484,11 +485,6 @@ static __init void xen_setup_pci_msi(void)
+ * in allocating the native domain and never use it.
+ */
+ x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain;
+- /*
+- * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely
+- * controlled by the hypervisor.
+- */
+- pci_msi_ignore_mask = 1;
+ }
+
+ #else /* CONFIG_PCI_MSI */
+diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
+index 2f647cac4cae3..4c8c2b57b5f61 100644
+--- a/drivers/pci/msi/msi.c
++++ b/drivers/pci/msi/msi.c
+@@ -10,12 +10,12 @@
+ #include <linux/err.h>
+ #include <linux/export.h>
+ #include <linux/irq.h>
++#include <linux/irqdomain.h>
+
+ #include "../pci.h"
+ #include "msi.h"
+
+ int pci_msi_enable = 1;
+-int pci_msi_ignore_mask;
+
+ /**
+ * pci_msi_supported - check whether MSI may be enabled on a device
+@@ -285,6 +285,8 @@ static void pci_msi_set_enable(struct pci_dev *dev, int enable)
+ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
+ struct irq_affinity_desc *masks)
+ {
++ const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
++ const struct msi_domain_info *info = d->host_data;
+ struct msi_desc desc;
+ u16 control;
+
+@@ -295,8 +297,7 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
+ /* Lies, damned lies, and MSIs */
+ if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
+ control |= PCI_MSI_FLAGS_MASKBIT;
+- /* Respect XEN's mask disabling */
+- if (pci_msi_ignore_mask)
++ if (info->flags & MSI_FLAG_NO_MASK)
+ control &= ~PCI_MSI_FLAGS_MASKBIT;
+
+ desc.nvec_used = nvec;
+@@ -604,12 +605,15 @@ static void __iomem *msix_map_region(struct pci_dev *dev,
+ */
+ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc)
+ {
++ const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
++ const struct msi_domain_info *info = d->host_data;
++
+ desc->nvec_used = 1;
+ desc->pci.msi_attrib.is_msix = 1;
+ desc->pci.msi_attrib.is_64 = 1;
+ desc->pci.msi_attrib.default_irq = dev->irq;
+ desc->pci.mask_base = dev->msix_base;
+- desc->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
++ desc->pci.msi_attrib.can_mask = !(info->flags & MSI_FLAG_NO_MASK) &&
+ !desc->pci.msi_attrib.is_virtual;
+
+ if (desc->pci.msi_attrib.can_mask) {
+@@ -659,9 +663,6 @@ static void msix_mask_all(void __iomem *base, int tsize)
+ u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
+ int i;
+
+- if (pci_msi_ignore_mask)
+- return;
+-
+ for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
+ writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
+ }
+@@ -714,6 +715,8 @@ static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries
+ static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
+ int nvec, struct irq_affinity *affd)
+ {
++ const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
++ const struct msi_domain_info *info = d->host_data;
+ int ret, tsize;
+ u16 control;
+
+@@ -744,15 +747,17 @@ static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
+ /* Disable INTX */
+ pci_intx_for_msi(dev, 0);
+
+- /*
+- * Ensure that all table entries are masked to prevent
+- * stale entries from firing in a crash kernel.
+- *
+- * Done late to deal with a broken Marvell NVME device
+- * which takes the MSI-X mask bits into account even
+- * when MSI-X is disabled, which prevents MSI delivery.
+- */
+- msix_mask_all(dev->msix_base, tsize);
++ if (!(info->flags & MSI_FLAG_NO_MASK)) {
++ /*
++ * Ensure that all table entries are masked to prevent
++ * stale entries from firing in a crash kernel.
++ *
++ * Done late to deal with a broken Marvell NVME device
++ * which takes the MSI-X mask bits into account even
++ * when MSI-X is disabled, which prevents MSI delivery.
++ */
++ msix_mask_all(dev->msix_base, tsize);
++ }
+ pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
+
+ pcibios_free_irq(dev);
+diff --git a/include/linux/msi.h b/include/linux/msi.h
+index b10093c4d00ea..59a421fc42bf0 100644
+--- a/include/linux/msi.h
++++ b/include/linux/msi.h
+@@ -73,7 +73,6 @@ struct msi_msg {
+ };
+ };
+
+-extern int pci_msi_ignore_mask;
+ /* Helper functions */
+ struct msi_desc;
+ struct pci_dev;
+@@ -556,6 +555,8 @@ enum {
+ MSI_FLAG_PCI_MSIX_ALLOC_DYN = (1 << 20),
+ /* PCI MSIs cannot be steered separately to CPU cores */
+ MSI_FLAG_NO_AFFINITY = (1 << 21),
++ /* Inhibit usage of entry masking */
++ MSI_FLAG_NO_MASK = (1 << 22),
+ };
+
+ /**
+diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c
+index 396a067a8a56b..7682c36cbccc6 100644
+--- a/kernel/irq/msi.c
++++ b/kernel/irq/msi.c
+@@ -1143,7 +1143,7 @@ static bool msi_check_reservation_mode(struct irq_domain *domain,
+ if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
+ return false;
+
+- if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
++ if (info->flags & MSI_FLAG_NO_MASK)
+ return false;
+
+ /*
+--
+2.39.5
+
--- /dev/null
+From c432e3b318b36504659ceedb6ca1450aaa390060 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Mar 2025 13:05:35 +0100
+Subject: PCI/MSI: Handle the NOMASK flag correctly for all PCI/MSI backends
+
+From: Thomas Gleixner <tglx@linutronix.de>
+
+[ Upstream commit 3ece3e8e5976c49c3f887e5923f998eabd54ff40 ]
+
+The conversion of the XEN specific global variable pci_msi_ignore_mask to a
+MSI domain flag, missed the facts that:
+
+ 1) Legacy architectures do not provide a interrupt domain
+ 2) Parent MSI domains do not necessarily have a domain info attached
+
+Both cases result in an unconditional NULL pointer dereference. This was
+unfortunatly missed in review and testing revealed it late.
+
+Cure this by using the existing pci_msi_domain_supports() helper, which
+handles all possible cases correctly.
+
+Fixes: c3164d2e0d18 ("PCI/MSI: Convert pci_msi_ignore_mask to per MSI domain flag")
+Reported-by: Daniel Gomez <da.gomez@kernel.org>
+Reported-by: Borislav Petkov <bp@alien8.de>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Reviewed-by: Juergen Gross <jgross@suse.com>
+Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Tested-by: Borislav Petkov <bp@alien8.de>
+Tested-by: Daniel Gomez <da.gomez@kernel.org>
+Link: https://lore.kernel.org/all/87iknwyp2o.ffs@tglx
+Closes: https://lore.kernel.org/all/qn7fzggcj6qe6r6gdbwcz23pzdz2jx64aldccmsuheabhmjgrt@tawf5nfwuvw7
+Stable-dep-of: cf761e3dacc6 ("PCI/MSI: Add an option to write MSIX ENTRY_DATA before any reads")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/msi/msi.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
+index 4c8c2b57b5f61..6569ba3577fe6 100644
+--- a/drivers/pci/msi/msi.c
++++ b/drivers/pci/msi/msi.c
+@@ -285,8 +285,6 @@ static void pci_msi_set_enable(struct pci_dev *dev, int enable)
+ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
+ struct irq_affinity_desc *masks)
+ {
+- const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
+- const struct msi_domain_info *info = d->host_data;
+ struct msi_desc desc;
+ u16 control;
+
+@@ -297,7 +295,7 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
+ /* Lies, damned lies, and MSIs */
+ if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
+ control |= PCI_MSI_FLAGS_MASKBIT;
+- if (info->flags & MSI_FLAG_NO_MASK)
++ if (pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY))
+ control &= ~PCI_MSI_FLAGS_MASKBIT;
+
+ desc.nvec_used = nvec;
+@@ -605,20 +603,18 @@ static void __iomem *msix_map_region(struct pci_dev *dev,
+ */
+ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc)
+ {
+- const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
+- const struct msi_domain_info *info = d->host_data;
+-
+ desc->nvec_used = 1;
+ desc->pci.msi_attrib.is_msix = 1;
+ desc->pci.msi_attrib.is_64 = 1;
+ desc->pci.msi_attrib.default_irq = dev->irq;
+ desc->pci.mask_base = dev->msix_base;
+- desc->pci.msi_attrib.can_mask = !(info->flags & MSI_FLAG_NO_MASK) &&
+- !desc->pci.msi_attrib.is_virtual;
+
+- if (desc->pci.msi_attrib.can_mask) {
++
++ if (!pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY) &&
++ !desc->pci.msi_attrib.is_virtual) {
+ void __iomem *addr = pci_msix_desc_addr(desc);
+
++ desc->pci.msi_attrib.can_mask = 1;
+ desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
+ }
+ }
+@@ -715,8 +711,6 @@ static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries
+ static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
+ int nvec, struct irq_affinity *affd)
+ {
+- const struct irq_domain *d = dev_get_msi_domain(&dev->dev);
+- const struct msi_domain_info *info = d->host_data;
+ int ret, tsize;
+ u16 control;
+
+@@ -747,7 +741,7 @@ static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
+ /* Disable INTX */
+ pci_intx_for_msi(dev, 0);
+
+- if (!(info->flags & MSI_FLAG_NO_MASK)) {
++ if (!pci_msi_domain_supports(dev, MSI_FLAG_NO_MASK, DENY_LEGACY)) {
+ /*
+ * Ensure that all table entries are masked to prevent
+ * stale entries from firing in a crash kernel.
+--
+2.39.5
+
--- /dev/null
+From 189b440ef1c427143ac03c99fa83b7d2e3a60809 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Mar 2025 17:49:20 +0100
+Subject: PM: EM: Address RCU-related sparse warnings
+
+From: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+
+[ Upstream commit 3ee7be9e10dd5f79448788b899591d4bd2bf0c19 ]
+
+The usage of __rcu in the Energy Model code is quite inconsistent
+which causes the following sparse warnings to trigger:
+
+kernel/power/energy_model.c:169:15: warning: incorrect type in assignment (different address spaces)
+kernel/power/energy_model.c:169:15: expected struct em_perf_table [noderef] __rcu *table
+kernel/power/energy_model.c:169:15: got struct em_perf_table *
+kernel/power/energy_model.c:171:9: warning: incorrect type in argument 1 (different address spaces)
+kernel/power/energy_model.c:171:9: expected struct callback_head *head
+kernel/power/energy_model.c:171:9: got struct callback_head [noderef] __rcu *
+kernel/power/energy_model.c:171:9: warning: cast removes address space '__rcu' of expression
+kernel/power/energy_model.c:182:19: warning: incorrect type in argument 1 (different address spaces)
+kernel/power/energy_model.c:182:19: expected struct kref *kref
+kernel/power/energy_model.c:182:19: got struct kref [noderef] __rcu *
+kernel/power/energy_model.c:200:15: warning: incorrect type in assignment (different address spaces)
+kernel/power/energy_model.c:200:15: expected struct em_perf_table [noderef] __rcu *table
+kernel/power/energy_model.c:200:15: got void *[assigned] _res
+kernel/power/energy_model.c:204:20: warning: incorrect type in argument 1 (different address spaces)
+kernel/power/energy_model.c:204:20: expected struct kref *kref
+kernel/power/energy_model.c:204:20: got struct kref [noderef] __rcu *
+kernel/power/energy_model.c:320:19: warning: incorrect type in argument 1 (different address spaces)
+kernel/power/energy_model.c:320:19: expected struct kref *kref
+kernel/power/energy_model.c:320:19: got struct kref [noderef] __rcu *
+kernel/power/energy_model.c:325:45: warning: incorrect type in argument 2 (different address spaces)
+kernel/power/energy_model.c:325:45: expected struct em_perf_state *table
+kernel/power/energy_model.c:325:45: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:425:45: warning: incorrect type in argument 3 (different address spaces)
+kernel/power/energy_model.c:425:45: expected struct em_perf_state *table
+kernel/power/energy_model.c:425:45: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:442:15: warning: incorrect type in argument 1 (different address spaces)
+kernel/power/energy_model.c:442:15: expected void const *objp
+kernel/power/energy_model.c:442:15: got struct em_perf_table [noderef] __rcu *[assigned] em_table
+kernel/power/energy_model.c:626:55: warning: incorrect type in argument 2 (different address spaces)
+kernel/power/energy_model.c:626:55: expected struct em_perf_state *table
+kernel/power/energy_model.c:626:55: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:681:16: warning: incorrect type in assignment (different address spaces)
+kernel/power/energy_model.c:681:16: expected struct em_perf_state *new_ps
+kernel/power/energy_model.c:681:16: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:699:37: warning: incorrect type in argument 2 (different address spaces)
+kernel/power/energy_model.c:699:37: expected struct em_perf_state *table
+kernel/power/energy_model.c:699:37: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:733:38: warning: incorrect type in argument 3 (different address spaces)
+kernel/power/energy_model.c:733:38: expected struct em_perf_state *table
+kernel/power/energy_model.c:733:38: got struct em_perf_state [noderef] __rcu *
+kernel/power/energy_model.c:855:53: warning: dereference of noderef expression
+kernel/power/energy_model.c:864:32: warning: dereference of noderef expression
+
+This is because the __rcu annotation for sparse is only applicable to
+pointers that need rcu_dereference() or equivalent for protection, which
+basically means pointers assigned with rcu_assign_pointer().
+
+Make all of the above sparse warnings go away by cleaning up the usage
+of __rcu and using rcu_dereference_protected() where applicable.
+
+Cc: All applicable <stable@vger.kernel.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
+Link: https://patch.msgid.link/5885405.DvuYhMxLoT@rjwysocki.net
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/energy_model.h | 12 +++++------
+ kernel/power/energy_model.c | 39 ++++++++++++++++++------------------
+ 2 files changed, 26 insertions(+), 25 deletions(-)
+
+diff --git a/include/linux/energy_model.h b/include/linux/energy_model.h
+index 1ff52020cf757..34498652f7802 100644
+--- a/include/linux/energy_model.h
++++ b/include/linux/energy_model.h
+@@ -163,13 +163,13 @@ struct em_data_callback {
+ struct em_perf_domain *em_cpu_get(int cpu);
+ struct em_perf_domain *em_pd_get(struct device *dev);
+ int em_dev_update_perf_domain(struct device *dev,
+- struct em_perf_table __rcu *new_table);
++ struct em_perf_table *new_table);
+ int em_dev_register_perf_domain(struct device *dev, unsigned int nr_states,
+ struct em_data_callback *cb, cpumask_t *span,
+ bool microwatts);
+ void em_dev_unregister_perf_domain(struct device *dev);
+-struct em_perf_table __rcu *em_table_alloc(struct em_perf_domain *pd);
+-void em_table_free(struct em_perf_table __rcu *table);
++struct em_perf_table *em_table_alloc(struct em_perf_domain *pd);
++void em_table_free(struct em_perf_table *table);
+ int em_dev_compute_costs(struct device *dev, struct em_perf_state *table,
+ int nr_states);
+ int em_dev_update_chip_binning(struct device *dev);
+@@ -365,14 +365,14 @@ static inline int em_pd_nr_perf_states(struct em_perf_domain *pd)
+ return 0;
+ }
+ static inline
+-struct em_perf_table __rcu *em_table_alloc(struct em_perf_domain *pd)
++struct em_perf_table *em_table_alloc(struct em_perf_domain *pd)
+ {
+ return NULL;
+ }
+-static inline void em_table_free(struct em_perf_table __rcu *table) {}
++static inline void em_table_free(struct em_perf_table *table) {}
+ static inline
+ int em_dev_update_perf_domain(struct device *dev,
+- struct em_perf_table __rcu *new_table)
++ struct em_perf_table *new_table)
+ {
+ return -EINVAL;
+ }
+diff --git a/kernel/power/energy_model.c b/kernel/power/energy_model.c
+index e303d938637f1..4e1778071d704 100644
+--- a/kernel/power/energy_model.c
++++ b/kernel/power/energy_model.c
+@@ -163,12 +163,8 @@ static void em_debug_remove_pd(struct device *dev) {}
+
+ static void em_release_table_kref(struct kref *kref)
+ {
+- struct em_perf_table __rcu *table;
+-
+ /* It was the last owner of this table so we can free */
+- table = container_of(kref, struct em_perf_table, kref);
+-
+- kfree_rcu(table, rcu);
++ kfree_rcu(container_of(kref, struct em_perf_table, kref), rcu);
+ }
+
+ /**
+@@ -177,7 +173,7 @@ static void em_release_table_kref(struct kref *kref)
+ *
+ * No return values.
+ */
+-void em_table_free(struct em_perf_table __rcu *table)
++void em_table_free(struct em_perf_table *table)
+ {
+ kref_put(&table->kref, em_release_table_kref);
+ }
+@@ -190,9 +186,9 @@ void em_table_free(struct em_perf_table __rcu *table)
+ * has a user.
+ * Returns allocated table or NULL.
+ */
+-struct em_perf_table __rcu *em_table_alloc(struct em_perf_domain *pd)
++struct em_perf_table *em_table_alloc(struct em_perf_domain *pd)
+ {
+- struct em_perf_table __rcu *table;
++ struct em_perf_table *table;
+ int table_size;
+
+ table_size = sizeof(struct em_perf_state) * pd->nr_perf_states;
+@@ -300,9 +296,9 @@ int em_dev_compute_costs(struct device *dev, struct em_perf_state *table,
+ * Return 0 on success or an error code on failure.
+ */
+ int em_dev_update_perf_domain(struct device *dev,
+- struct em_perf_table __rcu *new_table)
++ struct em_perf_table *new_table)
+ {
+- struct em_perf_table __rcu *old_table;
++ struct em_perf_table *old_table;
+ struct em_perf_domain *pd;
+
+ if (!dev)
+@@ -319,7 +315,8 @@ int em_dev_update_perf_domain(struct device *dev,
+
+ kref_get(&new_table->kref);
+
+- old_table = pd->em_table;
++ old_table = rcu_dereference_protected(pd->em_table,
++ lockdep_is_held(&em_pd_mutex));
+ rcu_assign_pointer(pd->em_table, new_table);
+
+ em_cpufreq_update_efficiencies(dev, new_table->state);
+@@ -391,7 +388,7 @@ static int em_create_pd(struct device *dev, int nr_states,
+ struct em_data_callback *cb, cpumask_t *cpus,
+ unsigned long flags)
+ {
+- struct em_perf_table __rcu *em_table;
++ struct em_perf_table *em_table;
+ struct em_perf_domain *pd;
+ struct device *cpu_dev;
+ int cpu, ret, num_cpus;
+@@ -551,6 +548,7 @@ int em_dev_register_perf_domain(struct device *dev, unsigned int nr_states,
+ struct em_data_callback *cb, cpumask_t *cpus,
+ bool microwatts)
+ {
++ struct em_perf_table *em_table;
+ unsigned long cap, prev_cap = 0;
+ unsigned long flags = 0;
+ int cpu, ret;
+@@ -621,7 +619,9 @@ int em_dev_register_perf_domain(struct device *dev, unsigned int nr_states,
+
+ dev->em_pd->flags |= flags;
+
+- em_cpufreq_update_efficiencies(dev, dev->em_pd->em_table->state);
++ em_table = rcu_dereference_protected(dev->em_pd->em_table,
++ lockdep_is_held(&em_pd_mutex));
++ em_cpufreq_update_efficiencies(dev, em_table->state);
+
+ em_debug_create_pd(dev);
+ dev_info(dev, "EM: created perf domain\n");
+@@ -658,7 +658,8 @@ void em_dev_unregister_perf_domain(struct device *dev)
+ mutex_lock(&em_pd_mutex);
+ em_debug_remove_pd(dev);
+
+- em_table_free(dev->em_pd->em_table);
++ em_table_free(rcu_dereference_protected(dev->em_pd->em_table,
++ lockdep_is_held(&em_pd_mutex)));
+
+ kfree(dev->em_pd);
+ dev->em_pd = NULL;
+@@ -666,9 +667,9 @@ void em_dev_unregister_perf_domain(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(em_dev_unregister_perf_domain);
+
+-static struct em_perf_table __rcu *em_table_dup(struct em_perf_domain *pd)
++static struct em_perf_table *em_table_dup(struct em_perf_domain *pd)
+ {
+- struct em_perf_table __rcu *em_table;
++ struct em_perf_table *em_table;
+ struct em_perf_state *ps, *new_ps;
+ int ps_size;
+
+@@ -690,7 +691,7 @@ static struct em_perf_table __rcu *em_table_dup(struct em_perf_domain *pd)
+ }
+
+ static int em_recalc_and_update(struct device *dev, struct em_perf_domain *pd,
+- struct em_perf_table __rcu *em_table)
++ struct em_perf_table *em_table)
+ {
+ int ret;
+
+@@ -721,7 +722,7 @@ static void em_adjust_new_capacity(struct device *dev,
+ struct em_perf_domain *pd,
+ u64 max_cap)
+ {
+- struct em_perf_table __rcu *em_table;
++ struct em_perf_table *em_table;
+
+ em_table = em_table_dup(pd);
+ if (!em_table) {
+@@ -812,7 +813,7 @@ static void em_update_workfn(struct work_struct *work)
+ */
+ int em_dev_update_chip_binning(struct device *dev)
+ {
+- struct em_perf_table __rcu *em_table;
++ struct em_perf_table *em_table;
+ struct em_perf_domain *pd;
+ int i, ret;
+
+--
+2.39.5
+
--- /dev/null
+From f93692661425801539bfcb4c9af74b827dab2394 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 18 Feb 2025 16:20:21 +0800
+Subject: PM: EM: use kfree_rcu() to simplify the code
+
+From: Li RongQing <lirongqing@baidu.com>
+
+[ Upstream commit 1618f635bdf56f3ac158171114e9bf18db234cbf ]
+
+The callback function of call_rcu() just calls kfree(), so use
+kfree_rcu() instead of call_rcu() + callback function.
+
+Signed-off-by: Li RongQing <lirongqing@baidu.com>
+Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
+Link: https://patch.msgid.link/20250218082021.2766-1-lirongqing@baidu.com
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Stable-dep-of: 3ee7be9e10dd ("PM: EM: Address RCU-related sparse warnings")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/power/energy_model.c | 10 +---------
+ 1 file changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/kernel/power/energy_model.c b/kernel/power/energy_model.c
+index 927cc55ba0b3d..e303d938637f1 100644
+--- a/kernel/power/energy_model.c
++++ b/kernel/power/energy_model.c
+@@ -161,14 +161,6 @@ static void em_debug_create_pd(struct device *dev) {}
+ static void em_debug_remove_pd(struct device *dev) {}
+ #endif
+
+-static void em_destroy_table_rcu(struct rcu_head *rp)
+-{
+- struct em_perf_table __rcu *table;
+-
+- table = container_of(rp, struct em_perf_table, rcu);
+- kfree(table);
+-}
+-
+ static void em_release_table_kref(struct kref *kref)
+ {
+ struct em_perf_table __rcu *table;
+@@ -176,7 +168,7 @@ static void em_release_table_kref(struct kref *kref)
+ /* It was the last owner of this table so we can free */
+ table = container_of(kref, struct em_perf_table, kref);
+
+- call_rcu(&table->rcu, em_destroy_table_rcu);
++ kfree_rcu(table, rcu);
+ }
+
+ /**
+--
+2.39.5
+
--- /dev/null
+From acc18c553ae5cd60d8e08151c2ed613a47c666aa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 13 Dec 2024 14:47:28 +0100
+Subject: s390/pci: Report PCI error recovery results via SCLP
+
+From: Niklas Schnelle <schnelle@linux.ibm.com>
+
+[ Upstream commit 4ec6054e7321dc24ebccaa08b3af0d590f5666e6 ]
+
+Add a mechanism with which the status of PCI error recovery runs
+is reported to the platform. Together with the status supply additional
+information that may aid in problem determination.
+
+Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
+Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com>
+Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
+Stable-dep-of: aa9f168d55dc ("s390/pci: Support mmap() of PCI resources except for ISM devices")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/s390/include/asm/sclp.h | 33 +++++++++++
+ arch/s390/pci/Makefile | 2 +-
+ arch/s390/pci/pci_event.c | 21 +++++--
+ arch/s390/pci/pci_report.c | 111 +++++++++++++++++++++++++++++++++++
+ arch/s390/pci/pci_report.h | 16 +++++
+ drivers/s390/char/sclp.h | 14 -----
+ drivers/s390/char/sclp_pci.c | 19 ------
+ 7 files changed, 178 insertions(+), 38 deletions(-)
+ create mode 100644 arch/s390/pci/pci_report.c
+ create mode 100644 arch/s390/pci/pci_report.h
+
+diff --git a/arch/s390/include/asm/sclp.h b/arch/s390/include/asm/sclp.h
+index ad17d91ad2e66..0efd6ab4473dd 100644
+--- a/arch/s390/include/asm/sclp.h
++++ b/arch/s390/include/asm/sclp.h
+@@ -16,6 +16,11 @@
+ /* 24 + 16 * SCLP_MAX_CORES */
+ #define EXT_SCCB_READ_CPU (3 * PAGE_SIZE)
+
++#define SCLP_ERRNOTIFY_AQ_RESET 0
++#define SCLP_ERRNOTIFY_AQ_REPAIR 1
++#define SCLP_ERRNOTIFY_AQ_INFO_LOG 2
++#define SCLP_ERRNOTIFY_AQ_OPTICS_DATA 3
++
+ #ifndef __ASSEMBLY__
+ #include <linux/uio.h>
+ #include <asm/chpid.h>
+@@ -111,6 +116,34 @@ struct sclp_info {
+ };
+ extern struct sclp_info sclp;
+
++struct sccb_header {
++ u16 length;
++ u8 function_code;
++ u8 control_mask[3];
++ u16 response_code;
++} __packed;
++
++struct evbuf_header {
++ u16 length;
++ u8 type;
++ u8 flags;
++ u16 _reserved;
++} __packed;
++
++struct err_notify_evbuf {
++ struct evbuf_header header;
++ u8 action;
++ u8 atype;
++ u32 fh;
++ u32 fid;
++ u8 data[];
++} __packed;
++
++struct err_notify_sccb {
++ struct sccb_header header;
++ struct err_notify_evbuf evbuf;
++} __packed;
++
+ struct zpci_report_error_header {
+ u8 version; /* Interface version byte */
+ u8 action; /* Action qualifier byte
+diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile
+index 2c21f0394c9ab..df73c5182990a 100644
+--- a/arch/s390/pci/Makefile
++++ b/arch/s390/pci/Makefile
+@@ -5,6 +5,6 @@
+
+ obj-$(CONFIG_PCI) += pci.o pci_irq.o pci_clp.o \
+ pci_event.o pci_debug.o pci_insn.o pci_mmio.o \
+- pci_bus.o pci_kvm_hook.o
++ pci_bus.o pci_kvm_hook.o pci_report.o
+ obj-$(CONFIG_PCI_IOV) += pci_iov.o
+ obj-$(CONFIG_SYSFS) += pci_sysfs.o
+diff --git a/arch/s390/pci/pci_event.c b/arch/s390/pci/pci_event.c
+index 7f7b732b3f3ef..7bd7721c1239a 100644
+--- a/arch/s390/pci/pci_event.c
++++ b/arch/s390/pci/pci_event.c
+@@ -16,6 +16,7 @@
+ #include <asm/sclp.h>
+
+ #include "pci_bus.h"
++#include "pci_report.h"
+
+ /* Content Code Description for PCI Function Error */
+ struct zpci_ccdf_err {
+@@ -169,6 +170,8 @@ static pci_ers_result_t zpci_event_do_reset(struct pci_dev *pdev,
+ static pci_ers_result_t zpci_event_attempt_error_recovery(struct pci_dev *pdev)
+ {
+ pci_ers_result_t ers_res = PCI_ERS_RESULT_DISCONNECT;
++ struct zpci_dev *zdev = to_zpci(pdev);
++ char *status_str = "success";
+ struct pci_driver *driver;
+
+ /*
+@@ -186,29 +189,37 @@ static pci_ers_result_t zpci_event_attempt_error_recovery(struct pci_dev *pdev)
+ if (is_passed_through(pdev)) {
+ pr_info("%s: Cannot be recovered in the host because it is a pass-through device\n",
+ pci_name(pdev));
++ status_str = "failed (pass-through)";
+ goto out_unlock;
+ }
+
+ driver = to_pci_driver(pdev->dev.driver);
+ if (!is_driver_supported(driver)) {
+- if (!driver)
++ if (!driver) {
+ pr_info("%s: Cannot be recovered because no driver is bound to the device\n",
+ pci_name(pdev));
+- else
++ status_str = "failed (no driver)";
++ } else {
+ pr_info("%s: The %s driver bound to the device does not support error recovery\n",
+ pci_name(pdev),
+ driver->name);
++ status_str = "failed (no driver support)";
++ }
+ goto out_unlock;
+ }
+
+ ers_res = zpci_event_notify_error_detected(pdev, driver);
+- if (ers_result_indicates_abort(ers_res))
++ if (ers_result_indicates_abort(ers_res)) {
++ status_str = "failed (abort on detection)";
+ goto out_unlock;
++ }
+
+ if (ers_res == PCI_ERS_RESULT_CAN_RECOVER) {
+ ers_res = zpci_event_do_error_state_clear(pdev, driver);
+- if (ers_result_indicates_abort(ers_res))
++ if (ers_result_indicates_abort(ers_res)) {
++ status_str = "failed (abort on MMIO enable)";
+ goto out_unlock;
++ }
+ }
+
+ if (ers_res == PCI_ERS_RESULT_NEED_RESET)
+@@ -217,6 +228,7 @@ static pci_ers_result_t zpci_event_attempt_error_recovery(struct pci_dev *pdev)
+ if (ers_res != PCI_ERS_RESULT_RECOVERED) {
+ pr_err("%s: Automatic recovery failed; operator intervention is required\n",
+ pci_name(pdev));
++ status_str = "failed (driver can't recover)";
+ goto out_unlock;
+ }
+
+@@ -225,6 +237,7 @@ static pci_ers_result_t zpci_event_attempt_error_recovery(struct pci_dev *pdev)
+ driver->err_handler->resume(pdev);
+ out_unlock:
+ pci_dev_unlock(pdev);
++ zpci_report_status(zdev, "recovery", status_str);
+
+ return ers_res;
+ }
+diff --git a/arch/s390/pci/pci_report.c b/arch/s390/pci/pci_report.c
+new file mode 100644
+index 0000000000000..2754c9c161f5b
+--- /dev/null
++++ b/arch/s390/pci/pci_report.c
+@@ -0,0 +1,111 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright IBM Corp. 2024
++ *
++ * Author(s):
++ * Niklas Schnelle <schnelle@linux.ibm.com>
++ *
++ */
++
++#define KMSG_COMPONENT "zpci"
++#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
++
++#include <linux/kernel.h>
++#include <linux/sprintf.h>
++#include <linux/pci.h>
++
++#include <asm/sclp.h>
++
++#include "pci_report.h"
++
++#define ZPCI_ERR_LOG_ID_KERNEL_REPORT 0x4714
++
++struct zpci_report_error_data {
++ u64 timestamp;
++ u64 err_log_id;
++ char log_data[];
++} __packed;
++
++#define ZPCI_REPORT_SIZE (PAGE_SIZE - sizeof(struct err_notify_sccb))
++#define ZPCI_REPORT_DATA_SIZE (ZPCI_REPORT_SIZE - sizeof(struct zpci_report_error_data))
++
++struct zpci_report_error {
++ struct zpci_report_error_header header;
++ struct zpci_report_error_data data;
++} __packed;
++
++static const char *zpci_state_str(pci_channel_state_t state)
++{
++ switch (state) {
++ case pci_channel_io_normal:
++ return "normal";
++ case pci_channel_io_frozen:
++ return "frozen";
++ case pci_channel_io_perm_failure:
++ return "permanent-failure";
++ default:
++ return "invalid";
++ };
++}
++
++/**
++ * zpci_report_status - Report the status of operations on a PCI device
++ * @zdev: The PCI device for which to report status
++ * @operation: A string representing the operation reported
++ * @status: A string representing the status of the operation
++ *
++ * This function creates a human readable report about an operation such as
++ * PCI device recovery and forwards this to the platform using the SCLP Write
++ * Event Data mechanism. Besides the operation and status strings the report
++ * also contains additional information about the device deemed useful for
++ * debug such as the currently bound device driver, if any, and error state.
++ *
++ * Return: 0 on success an error code < 0 otherwise.
++ */
++int zpci_report_status(struct zpci_dev *zdev, const char *operation, const char *status)
++{
++ struct zpci_report_error *report;
++ struct pci_driver *driver = NULL;
++ struct pci_dev *pdev = NULL;
++ char *buf, *end;
++ int ret;
++
++ if (!zdev || !zdev->zbus)
++ return -ENODEV;
++
++ /* Protected virtualization hosts get nothing from us */
++ if (prot_virt_guest)
++ return -ENODATA;
++
++ report = (void *)get_zeroed_page(GFP_KERNEL);
++ if (!report)
++ return -ENOMEM;
++ if (zdev->zbus->bus)
++ pdev = pci_get_slot(zdev->zbus->bus, zdev->devfn);
++ if (pdev)
++ driver = to_pci_driver(pdev->dev.driver);
++
++ buf = report->data.log_data;
++ end = report->data.log_data + ZPCI_REPORT_DATA_SIZE;
++ buf += scnprintf(buf, end - buf, "report: %s\n", operation);
++ buf += scnprintf(buf, end - buf, "status: %s\n", status);
++ buf += scnprintf(buf, end - buf, "state: %s\n",
++ (pdev) ? zpci_state_str(pdev->error_state) : "n/a");
++ buf += scnprintf(buf, end - buf, "driver: %s\n", (driver) ? driver->name : "n/a");
++
++ report->header.version = 1;
++ report->header.action = SCLP_ERRNOTIFY_AQ_INFO_LOG;
++ report->header.length = buf - (char *)&report->data;
++ report->data.timestamp = ktime_get_clocktai_seconds();
++ report->data.err_log_id = ZPCI_ERR_LOG_ID_KERNEL_REPORT;
++
++ ret = sclp_pci_report(&report->header, zdev->fh, zdev->fid);
++ if (ret)
++ pr_err("Reporting PCI status failed with code %d\n", ret);
++ else
++ pr_info("Reported PCI device status\n");
++
++ free_page((unsigned long)report);
++
++ return ret;
++}
+diff --git a/arch/s390/pci/pci_report.h b/arch/s390/pci/pci_report.h
+new file mode 100644
+index 0000000000000..e08003d51a972
+--- /dev/null
++++ b/arch/s390/pci/pci_report.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright IBM Corp. 2024
++ *
++ * Author(s):
++ * Niklas Schnelle <schnelle@linux.ibm.com>
++ *
++ */
++#ifndef __S390_PCI_REPORT_H
++#define __S390_PCI_REPORT_H
++
++struct zpci_dev;
++
++int zpci_report_status(struct zpci_dev *zdev, const char *operation, const char *status);
++
++#endif /* __S390_PCI_REPORT_H */
+diff --git a/drivers/s390/char/sclp.h b/drivers/s390/char/sclp.h
+index 6a23ec286c702..25fd4d8547483 100644
+--- a/drivers/s390/char/sclp.h
++++ b/drivers/s390/char/sclp.h
+@@ -84,13 +84,6 @@ typedef unsigned int sclp_cmdw_t;
+
+ typedef u64 sccb_mask_t;
+
+-struct sccb_header {
+- u16 length;
+- u8 function_code;
+- u8 control_mask[3];
+- u16 response_code;
+-} __attribute__((packed));
+-
+ struct init_sccb {
+ struct sccb_header header;
+ u16 _reserved;
+@@ -237,13 +230,6 @@ struct gds_vector {
+ u16 gds_id;
+ } __attribute__((packed));
+
+-struct evbuf_header {
+- u16 length;
+- u8 type;
+- u8 flags;
+- u16 _reserved;
+-} __attribute__((packed));
+-
+ struct sclp_req {
+ struct list_head list; /* list_head for request queueing. */
+ sclp_cmdw_t command; /* sclp command to execute */
+diff --git a/drivers/s390/char/sclp_pci.c b/drivers/s390/char/sclp_pci.c
+index c3466a8c56bb5..56400886f7fca 100644
+--- a/drivers/s390/char/sclp_pci.c
++++ b/drivers/s390/char/sclp_pci.c
+@@ -24,30 +24,11 @@
+
+ #define SCLP_ATYPE_PCI 2
+
+-#define SCLP_ERRNOTIFY_AQ_RESET 0
+-#define SCLP_ERRNOTIFY_AQ_REPAIR 1
+-#define SCLP_ERRNOTIFY_AQ_INFO_LOG 2
+-#define SCLP_ERRNOTIFY_AQ_OPTICS_DATA 3
+-
+ static DEFINE_MUTEX(sclp_pci_mutex);
+ static struct sclp_register sclp_pci_event = {
+ .send_mask = EVTYP_ERRNOTIFY_MASK,
+ };
+
+-struct err_notify_evbuf {
+- struct evbuf_header header;
+- u8 action;
+- u8 atype;
+- u32 fh;
+- u32 fid;
+- u8 data[];
+-} __packed;
+-
+-struct err_notify_sccb {
+- struct sccb_header header;
+- struct err_notify_evbuf evbuf;
+-} __packed;
+-
+ struct pci_cfg_sccb {
+ struct sccb_header header;
+ u8 atype; /* adapter type */
+--
+2.39.5
+
--- /dev/null
+From ea19bdc1c71f24fd0df0c5ffafd28301e47414b4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Feb 2025 13:07:47 +0100
+Subject: s390/pci: Support mmap() of PCI resources except for ISM devices
+
+From: Niklas Schnelle <schnelle@linux.ibm.com>
+
+[ Upstream commit aa9f168d55dc47c0de564f7dfe0e90467c9fee71 ]
+
+So far s390 does not allow mmap() of PCI resources to user-space via the
+usual mechanisms, though it does use it for RDMA. For the PCI sysfs
+resource files and /proc/bus/pci it defines neither HAVE_PCI_MMAP nor
+ARCH_GENERIC_PCI_MMAP_RESOURCE. For vfio-pci s390 previously relied on
+disabled VFIO_PCI_MMAP and now relies on setting pdev->non_mappable_bars
+for all devices.
+
+This is partly because access to mapped PCI resources from user-space
+requires special PCI load/store memory-I/O (MIO) instructions, or the
+special MMIO syscalls when these are not available. Still, such access is
+possible and useful not just for RDMA, in fact not being able to mmap() PCI
+resources has previously caused extra work when testing devices.
+
+One thing that doesn't work with PCI resources mapped to user-space though
+is the s390 specific virtual ISM device. Not only because the BAR size of
+256 TiB prevents mapping the whole BAR but also because access requires use
+of the legacy PCI instructions which are not accessible to user-space on
+systems with the newer MIO PCI instructions.
+
+Now with the pdev->non_mappable_bars flag ISM can be excluded from mapping
+its resources while making this functionality available for all other PCI
+devices. To this end introduce a minimal implementation of PCI_QUIRKS and
+use that to set pdev->non_mappable_bars for ISM devices only. Then also set
+ARCH_GENERIC_PCI_MMAP_RESOURCE to take advantage of the generic
+implementation of pci_mmap_resource_range() enabling only the newer sysfs
+mmap() interface. This follows the recommendation in
+Documentation/PCI/sysfs-pci.rst.
+
+Link: https://lore.kernel.org/r/20250226-vfio_pci_mmap-v7-3-c5c0f1d26efd@linux.ibm.com
+Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/s390/Kconfig | 4 +---
+ arch/s390/include/asm/pci.h | 3 +++
+ arch/s390/pci/Makefile | 2 +-
+ arch/s390/pci/pci_fixup.c | 23 +++++++++++++++++++++++
+ drivers/s390/net/ism_drv.c | 1 -
+ include/linux/pci_ids.h | 1 +
+ 6 files changed, 29 insertions(+), 5 deletions(-)
+ create mode 100644 arch/s390/pci/pci_fixup.c
+
+diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
+index 62f2c9e8e05f7..b9f70927c1ed8 100644
+--- a/arch/s390/Kconfig
++++ b/arch/s390/Kconfig
+@@ -41,9 +41,6 @@ config AUDIT_ARCH
+ config NO_IOPORT_MAP
+ def_bool y
+
+-config PCI_QUIRKS
+- def_bool n
+-
+ config ARCH_SUPPORTS_UPROBES
+ def_bool y
+
+@@ -237,6 +234,7 @@ config S390
+ select PCI_DOMAINS if PCI
+ select PCI_MSI if PCI
+ select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
++ select PCI_QUIRKS if PCI
+ select SPARSE_IRQ
+ select SWIOTLB
+ select SYSCTL_EXCEPTION_TRACE
+diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
+index 83789e39d1d5e..8b11d37fd0349 100644
+--- a/arch/s390/include/asm/pci.h
++++ b/arch/s390/include/asm/pci.h
+@@ -11,6 +11,9 @@
+ #include <asm/pci_insn.h>
+ #include <asm/sclp.h>
+
++#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
++#define arch_can_pci_mmap_wc() 1
++
+ #define PCIBIOS_MIN_IO 0x1000
+ #define PCIBIOS_MIN_MEM 0x10000000
+
+diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile
+index df73c5182990a..1810e0944a4ed 100644
+--- a/arch/s390/pci/Makefile
++++ b/arch/s390/pci/Makefile
+@@ -5,6 +5,6 @@
+
+ obj-$(CONFIG_PCI) += pci.o pci_irq.o pci_clp.o \
+ pci_event.o pci_debug.o pci_insn.o pci_mmio.o \
+- pci_bus.o pci_kvm_hook.o pci_report.o
++ pci_bus.o pci_kvm_hook.o pci_report.o pci_fixup.o
+ obj-$(CONFIG_PCI_IOV) += pci_iov.o
+ obj-$(CONFIG_SYSFS) += pci_sysfs.o
+diff --git a/arch/s390/pci/pci_fixup.c b/arch/s390/pci/pci_fixup.c
+new file mode 100644
+index 0000000000000..35688b6450983
+--- /dev/null
++++ b/arch/s390/pci/pci_fixup.c
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Exceptions for specific devices,
++ *
++ * Copyright IBM Corp. 2025
++ *
++ * Author(s):
++ * Niklas Schnelle <schnelle@linux.ibm.com>
++ */
++#include <linux/pci.h>
++
++static void zpci_ism_bar_no_mmap(struct pci_dev *pdev)
++{
++ /*
++ * ISM's BAR is special. Drivers written for ISM know
++ * how to handle this but others need to be aware of their
++ * special nature e.g. to prevent attempts to mmap() it.
++ */
++ pdev->non_mappable_bars = 1;
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM,
++ PCI_DEVICE_ID_IBM_ISM,
++ zpci_ism_bar_no_mmap);
+diff --git a/drivers/s390/net/ism_drv.c b/drivers/s390/net/ism_drv.c
+index 2f34761e64135..60ed70a39d2cc 100644
+--- a/drivers/s390/net/ism_drv.c
++++ b/drivers/s390/net/ism_drv.c
+@@ -20,7 +20,6 @@
+ MODULE_DESCRIPTION("ISM driver for s390");
+ MODULE_LICENSE("GPL");
+
+-#define PCI_DEVICE_ID_IBM_ISM 0x04ED
+ #define DRV_NAME "ism"
+
+ static const struct pci_device_id ism_device_table[] = {
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index c395b3c5c05cf..89896e82e40d8 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -517,6 +517,7 @@
+ #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251
+ #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
+ #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252
++#define PCI_DEVICE_ID_IBM_ISM 0x04ed
+
+ #define PCI_SUBVENDOR_ID_IBM 0x1014
+ #define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT 0x03d4
+--
+2.39.5
+
--- /dev/null
+From b0f229580e52d4cbf0c613fb65ddb70ba7be826c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Oct 2024 15:07:27 +0200
+Subject: s390/sclp: Allow user-space to provide PCI reports for optical
+ modules
+
+From: Niklas Schnelle <schnelle@linux.ibm.com>
+
+[ Upstream commit e9ab04490667249633fb397be17db46a8fa6d130 ]
+
+The new SCLP action qualifier 3 is used by user-space code to provide
+optical module monitoring data to the platform.
+
+Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com>
+Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
+Stable-dep-of: aa9f168d55dc ("s390/pci: Support mmap() of PCI resources except for ISM devices")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/s390/char/sclp_pci.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/s390/char/sclp_pci.c b/drivers/s390/char/sclp_pci.c
+index a3e5a5fb0c1e7..c3466a8c56bb5 100644
+--- a/drivers/s390/char/sclp_pci.c
++++ b/drivers/s390/char/sclp_pci.c
+@@ -27,6 +27,7 @@
+ #define SCLP_ERRNOTIFY_AQ_RESET 0
+ #define SCLP_ERRNOTIFY_AQ_REPAIR 1
+ #define SCLP_ERRNOTIFY_AQ_INFO_LOG 2
++#define SCLP_ERRNOTIFY_AQ_OPTICS_DATA 3
+
+ static DEFINE_MUTEX(sclp_pci_mutex);
+ static struct sclp_register sclp_pci_event = {
+@@ -116,6 +117,7 @@ static int sclp_pci_check_report(struct zpci_report_error_header *report)
+ case SCLP_ERRNOTIFY_AQ_RESET:
+ case SCLP_ERRNOTIFY_AQ_REPAIR:
+ case SCLP_ERRNOTIFY_AQ_INFO_LOG:
++ case SCLP_ERRNOTIFY_AQ_OPTICS_DATA:
+ break;
+ default:
+ return -EINVAL;
+--
+2.39.5
+
--- /dev/null
+From ca9cbec2d5931b716232dd77c7dba127a510de32 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 31 Oct 2024 15:00:28 +0000
+Subject: scsi: ufs: exynos: Add gs101_ufs_drv_init() hook and enable
+ WriteBooster
+
+From: Peter Griffin <peter.griffin@linaro.org>
+
+[ Upstream commit 9cc4a4a5767756b1ebe45a76c4673432545ea70e ]
+
+Factor out the common code into a new exynos_ufs_shareability() function
+and provide a dedicated gs101_drv_init() hook.
+
+This allows us to enable WriteBooster capability (UFSHCD_CAP_WB_EN) in a
+way that doesn't effect other SoCs supported in this driver.
+
+WriteBooster improves write speeds by enabling a pseudo SLC cache. Using
+the 'fio seqwrite' test we can achieve speeds of 945MB/s with this
+feature enabled (until the cache is exhausted) before dropping back to
+~260MB/s (which are the speeds we see without the WriteBooster feature
+enabled).
+
+Assuming the UFSHCD_CAP_WB_EN capability is set by the host then
+WriteBooster can also be enabled and disabled via sysfs so it is
+possible for the system to only enable it when extra write performance
+is required.
+
+Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
+Link: https://lore.kernel.org/r/20241031150033.3440894-10-peter.griffin@linaro.org
+Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 68f5ef7eebf0 ("scsi: ufs: exynos: Move UFS shareability value to drvdata")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-exynos.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
+index 8adf11f37c0d7..149c8127cf556 100644
+--- a/drivers/ufs/host/ufs-exynos.c
++++ b/drivers/ufs/host/ufs-exynos.c
+@@ -198,7 +198,7 @@ static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
+ exynos_ufs_ctrl_clkstop(ufs, false);
+ }
+
+-static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
++static int exynos_ufs_shareability(struct exynos_ufs *ufs)
+ {
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+
+@@ -214,6 +214,21 @@ static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
+ return 0;
+ }
+
++static int gs101_ufs_drv_init(struct exynos_ufs *ufs)
++{
++ struct ufs_hba *hba = ufs->hba;
++
++ /* Enable WriteBooster */
++ hba->caps |= UFSHCD_CAP_WB_EN;
++
++ return exynos_ufs_shareability(ufs);
++}
++
++static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
++{
++ return exynos_ufs_shareability(ufs);
++}
++
+ static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
+ {
+ struct ufs_hba *hba = ufs->hba;
+@@ -2128,7 +2143,7 @@ static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_UFSPR_SECURE |
+ EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
+- .drv_init = exynosauto_ufs_drv_init,
++ .drv_init = gs101_ufs_drv_init,
+ .pre_link = gs101_ufs_pre_link,
+ .post_link = gs101_ufs_post_link,
+ .pre_pwr_change = gs101_ufs_pre_pwr_change,
+--
+2.39.5
+
--- /dev/null
+From 65c7bae3bfe24a0dbfc5b6046f64c1d7f6b32810 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Mar 2025 15:30:20 +0000
+Subject: scsi: ufs: exynos: Disable iocc if dma-coherent property isn't set
+
+From: Peter Griffin <peter.griffin@linaro.org>
+
+[ Upstream commit f92bb7436802f8eb7ee72dc911a33c8897fde366 ]
+
+If dma-coherent property isn't set then descriptors are non-cacheable
+and the iocc shareability bits should be disabled. Without this UFS can
+end up in an incompatible configuration and suffer from random cache
+related stability issues.
+
+Suggested-by: Bart Van Assche <bvanassche@acm.org>
+Fixes: cc52e15397cc ("scsi: ufs: ufs-exynos: Support ExynosAuto v9 UFS")
+Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
+Link: https://lore.kernel.org/r/20250319-exynos-ufs-stability-fixes-v2-3-96722cc2ba1b@linaro.org
+Cc: Chanho Park <chanho61.park@samsung.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-exynos.c | 17 +++++++++++++----
+ drivers/ufs/host/ufs-exynos.h | 3 ++-
+ 2 files changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
+index 453f1dee103c8..fd1ebb4fcd96c 100644
+--- a/drivers/ufs/host/ufs-exynos.c
++++ b/drivers/ufs/host/ufs-exynos.c
+@@ -210,8 +210,8 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs)
+ /* IO Coherency setting */
+ if (ufs->sysreg) {
+ return regmap_update_bits(ufs->sysreg,
+- ufs->shareability_reg_offset,
+- ufs->iocc_mask, ufs->iocc_mask);
++ ufs->iocc_offset,
++ ufs->iocc_mask, ufs->iocc_val);
+ }
+
+ attr->tx_dif_p_nsec = 3200000;
+@@ -1147,13 +1147,22 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
+ ufs->sysreg = NULL;
+ else {
+ if (of_property_read_u32_index(np, "samsung,sysreg", 1,
+- &ufs->shareability_reg_offset)) {
++ &ufs->iocc_offset)) {
+ dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
+- ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET;
++ ufs->iocc_offset = UFS_SHAREABILITY_OFFSET;
+ }
+ }
+
+ ufs->iocc_mask = ufs->drv_data->iocc_mask;
++ /*
++ * no 'dma-coherent' property means the descriptors are
++ * non-cacheable so iocc shareability should be disabled.
++ */
++ if (of_dma_is_coherent(dev->of_node))
++ ufs->iocc_val = ufs->iocc_mask;
++ else
++ ufs->iocc_val = 0;
++
+ ufs->pclk_avail_min = PCLK_AVAIL_MIN;
+ ufs->pclk_avail_max = PCLK_AVAIL_MAX;
+
+diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
+index ad49d9cdd5c12..d0b3df221503c 100644
+--- a/drivers/ufs/host/ufs-exynos.h
++++ b/drivers/ufs/host/ufs-exynos.h
+@@ -231,8 +231,9 @@ struct exynos_ufs {
+ ktime_t entry_hibern8_t;
+ const struct exynos_ufs_drv_data *drv_data;
+ struct regmap *sysreg;
+- u32 shareability_reg_offset;
++ u32 iocc_offset;
+ u32 iocc_mask;
++ u32 iocc_val;
+
+ u32 opts;
+ #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
+--
+2.39.5
+
--- /dev/null
+From 49007ffb28da8f99e0c399a26d6da09172c0c32f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 19 Mar 2025 15:30:19 +0000
+Subject: scsi: ufs: exynos: Move UFS shareability value to drvdata
+
+From: Peter Griffin <peter.griffin@linaro.org>
+
+[ Upstream commit 68f5ef7eebf0f41df4d38ea55a54c2462af1e3d6 ]
+
+gs101 I/O coherency shareability bits differ from exynosauto SoC. To
+support both SoCs move this info the SoC drvdata.
+
+Currently both the value and mask are the same for both gs101 and
+exynosauto, thus we use the same value.
+
+Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
+Link: https://lore.kernel.org/r/20250319-exynos-ufs-stability-fixes-v2-2-96722cc2ba1b@linaro.org
+Fixes: d11e0a318df8 ("scsi: ufs: exynos: Add support for Tensor gs101 SoC")
+Cc: stable@vger.kernel.org
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-exynos.c | 20 ++++++++++++++------
+ drivers/ufs/host/ufs-exynos.h | 2 ++
+ 2 files changed, 16 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
+index 149c8127cf556..453f1dee103c8 100644
+--- a/drivers/ufs/host/ufs-exynos.c
++++ b/drivers/ufs/host/ufs-exynos.c
+@@ -86,11 +86,16 @@
+ UIC_TRANSPORT_NO_CONNECTION_RX |\
+ UIC_TRANSPORT_BAD_TC)
+
+-/* FSYS UFS Shareability */
+-#define UFS_WR_SHARABLE BIT(2)
+-#define UFS_RD_SHARABLE BIT(1)
+-#define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
+-#define UFS_SHAREABILITY_OFFSET 0x710
++/* UFS Shareability */
++#define UFS_EXYNOSAUTO_WR_SHARABLE BIT(2)
++#define UFS_EXYNOSAUTO_RD_SHARABLE BIT(1)
++#define UFS_EXYNOSAUTO_SHARABLE (UFS_EXYNOSAUTO_WR_SHARABLE | \
++ UFS_EXYNOSAUTO_RD_SHARABLE)
++#define UFS_GS101_WR_SHARABLE BIT(1)
++#define UFS_GS101_RD_SHARABLE BIT(0)
++#define UFS_GS101_SHARABLE (UFS_GS101_WR_SHARABLE | \
++ UFS_GS101_RD_SHARABLE)
++#define UFS_SHAREABILITY_OFFSET 0x710
+
+ /* Multi-host registers */
+ #define MHCTRL 0xC4
+@@ -206,7 +211,7 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs)
+ if (ufs->sysreg) {
+ return regmap_update_bits(ufs->sysreg,
+ ufs->shareability_reg_offset,
+- UFS_SHARABLE, UFS_SHARABLE);
++ ufs->iocc_mask, ufs->iocc_mask);
+ }
+
+ attr->tx_dif_p_nsec = 3200000;
+@@ -1148,6 +1153,7 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
+ }
+ }
+
++ ufs->iocc_mask = ufs->drv_data->iocc_mask;
+ ufs->pclk_avail_min = PCLK_AVAIL_MIN;
+ ufs->pclk_avail_max = PCLK_AVAIL_MAX;
+
+@@ -2021,6 +2027,7 @@ static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
+ .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
++ .iocc_mask = UFS_EXYNOSAUTO_SHARABLE,
+ .drv_init = exynosauto_ufs_drv_init,
+ .post_hce_enable = exynosauto_ufs_post_hce_enable,
+ .pre_link = exynosauto_ufs_pre_link,
+@@ -2143,6 +2150,7 @@ static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_UFSPR_SECURE |
+ EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
++ .iocc_mask = UFS_GS101_SHARABLE,
+ .drv_init = gs101_ufs_drv_init,
+ .pre_link = gs101_ufs_pre_link,
+ .post_link = gs101_ufs_post_link,
+diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
+index 9670dc138d1e4..ad49d9cdd5c12 100644
+--- a/drivers/ufs/host/ufs-exynos.h
++++ b/drivers/ufs/host/ufs-exynos.h
+@@ -181,6 +181,7 @@ struct exynos_ufs_drv_data {
+ struct exynos_ufs_uic_attr *uic_attr;
+ unsigned int quirks;
+ unsigned int opts;
++ u32 iocc_mask;
+ /* SoC's specific operations */
+ int (*drv_init)(struct exynos_ufs *ufs);
+ int (*pre_link)(struct exynos_ufs *ufs);
+@@ -231,6 +232,7 @@ struct exynos_ufs {
+ const struct exynos_ufs_drv_data *drv_data;
+ struct regmap *sysreg;
+ u32 shareability_reg_offset;
++ u32 iocc_mask;
+
+ u32 opts;
+ #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
+--
+2.39.5
+
--- /dev/null
+From 08c0ccd6954fb56c68657012e5777632a70a9c8f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 31 Oct 2024 15:00:20 +0000
+Subject: scsi: ufs: exynos: Remove empty drv_init method
+
+From: Tudor Ambarus <tudor.ambarus@linaro.org>
+
+[ Upstream commit 07c2a737504457c41678c5c30abe9107cd28dce6 ]
+
+Remove empty method. When the method is not set, the call is not made,
+saving a few cycles.
+
+Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
+Link: https://lore.kernel.org/r/20241031150033.3440894-2-peter.griffin@linaro.org
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 68f5ef7eebf0 ("scsi: ufs: exynos: Move UFS shareability value to drvdata")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-exynos.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
+index f2cbfc2d399cd..69fcfffb1c89d 100644
+--- a/drivers/ufs/host/ufs-exynos.c
++++ b/drivers/ufs/host/ufs-exynos.c
+@@ -198,11 +198,6 @@ static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
+ exynos_ufs_ctrl_clkstop(ufs, false);
+ }
+
+-static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+-{
+- return 0;
+-}
+-
+ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+ {
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+@@ -2044,7 +2039,6 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
+ EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
+ EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
+- .drv_init = exynos7_ufs_drv_init,
+ .pre_link = exynos7_ufs_pre_link,
+ .post_link = exynos7_ufs_post_link,
+ .pre_pwr_change = exynos7_ufs_pre_pwr_change,
+--
+2.39.5
+
--- /dev/null
+From 762c7713ae0fdb2441e9901ab32751b426668fe6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 31 Oct 2024 15:00:21 +0000
+Subject: scsi: ufs: exynos: Remove superfluous function parameter
+
+From: Tudor Ambarus <tudor.ambarus@linaro.org>
+
+[ Upstream commit afd613ca2c60d0a970d434bc73e1ddcdb925c799 ]
+
+The pointer to device can be obtained from ufs->hba->dev, remove
+superfluous function parameter.
+
+Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
+Link: https://lore.kernel.org/r/20241031150033.3440894-3-peter.griffin@linaro.org
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Stable-dep-of: 68f5ef7eebf0 ("scsi: ufs: exynos: Move UFS shareability value to drvdata")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-exynos.c | 4 ++--
+ drivers/ufs/host/ufs-exynos.h | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
+index 69fcfffb1c89d..8adf11f37c0d7 100644
+--- a/drivers/ufs/host/ufs-exynos.c
++++ b/drivers/ufs/host/ufs-exynos.c
+@@ -198,7 +198,7 @@ static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
+ exynos_ufs_ctrl_clkstop(ufs, false);
+ }
+
+-static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
++static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
+ {
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+
+@@ -1433,7 +1433,7 @@ static int exynos_ufs_init(struct ufs_hba *hba)
+ exynos_ufs_fmp_init(hba, ufs);
+
+ if (ufs->drv_data->drv_init) {
+- ret = ufs->drv_data->drv_init(dev, ufs);
++ ret = ufs->drv_data->drv_init(ufs);
+ if (ret) {
+ dev_err(dev, "failed to init drv-data\n");
+ goto out;
+diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
+index 1646c4a9bb088..9670dc138d1e4 100644
+--- a/drivers/ufs/host/ufs-exynos.h
++++ b/drivers/ufs/host/ufs-exynos.h
+@@ -182,7 +182,7 @@ struct exynos_ufs_drv_data {
+ unsigned int quirks;
+ unsigned int opts;
+ /* SoC's specific operations */
+- int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
++ int (*drv_init)(struct exynos_ufs *ufs);
+ int (*pre_link)(struct exynos_ufs *ufs);
+ int (*post_link)(struct exynos_ufs *ufs);
+ int (*pre_pwr_change)(struct exynos_ufs *ufs,
+--
+2.39.5
+
--- /dev/null
+From e4e042222441bb9a44003a751c98d4a80c32c3a9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 17 Jan 2025 14:18:52 +0000
+Subject: scsi: ufs: qcom: fix dev reference leaked through of_qcom_ice_get
+
+From: Tudor Ambarus <tudor.ambarus@linaro.org>
+
+[ Upstream commit ded40f32b55f7f2f4ed9627dd3c37a1fe89ed8c6 ]
+
+The driver leaks the device reference taken with
+of_find_device_by_node(). Fix the leak by using devm_of_qcom_ice_get().
+
+Fixes: 56541c7c4468 ("scsi: ufs: ufs-qcom: Switch to the new ICE API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
+Acked-by: Martin K. Petersen <martin.petersen@oracle.com> # SCSI
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20250117-qcom-ice-fix-dev-leak-v2-3-1ffa5b6884cb@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/ufs/host/ufs-qcom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
+index e12c5f9f79563..4557b1bcd6356 100644
+--- a/drivers/ufs/host/ufs-qcom.c
++++ b/drivers/ufs/host/ufs-qcom.c
+@@ -118,7 +118,7 @@ static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
+ struct device *dev = hba->dev;
+ struct qcom_ice *ice;
+
+- ice = of_qcom_ice_get(dev);
++ ice = devm_of_qcom_ice_get(dev);
+ if (ice == ERR_PTR(-EOPNOTSUPP)) {
+ dev_warn(dev, "Disabling inline encryption support\n");
+ ice = NULL;
+--
+2.39.5
+
module-sign-with-sha512-instead-of-sha1-by-default.patch
+tracing-add-__print_dynamic_array-helper.patch
+tracing-verify-event-formats-that-have-p.patch
+mm-vmscan-don-t-try-to-reclaim-hwpoison-folio.patch
+soc-qcom-ice-introduce-devm_of_qcom_ice_get.patch
+mmc-sdhci-msm-fix-dev-reference-leaked-through-of_qc.patch
+pm-em-use-kfree_rcu-to-simplify-the-code.patch
+pm-em-address-rcu-related-sparse-warnings.patch
+media-i2c-imx214-use-subdev-active-state.patch
+media-i2c-imx214-simplify-with-dev_err_probe.patch
+media-i2c-imx214-convert-to-cci-register-access-help.patch
+media-i2c-imx214-replace-register-addresses-with-mac.patch
+media-i2c-imx214-check-number-of-lanes-from-device-t.patch
+media-i2c-imx214-fix-link-frequency-validation.patch
+media-ov08x40-move-ov08x40_identify_module-function-.patch
+media-ov08x40-add-missing-ov08x40_identify_module-ca.patch
+block-remove-the-write_hint-field-from-struct-reques.patch
+block-remove-the-ioprio-field-from-struct-request.patch
+block-make-sure-nr_integrity_segments-is-cloned-in-b.patch
+net-dsa-mv88e6xxx-fix-vtu-methods-for-6320-family.patch
+iio-adc-ad7768-1-move-setting-of-val-a-bit-later-to-.patch
+iio-adc-ad7768-1-fix-conversion-result-sign.patch
+arm64-dts-ti-refactor-j784s4-soc-files-to-a-common-f.patch
+arm64-dts-ti-k3-j784s4-j742s2-main-common-fix-serdes.patch
+of-resolver-simplify-of_resolve_phandles-using-__fre.patch
+of-resolver-fix-device-node-refcount-leakage-in-of_r.patch
+scsi-ufs-qcom-fix-dev-reference-leaked-through-of_qc.patch
+s390-sclp-allow-user-space-to-provide-pci-reports-fo.patch
+s390-pci-report-pci-error-recovery-results-via-sclp.patch
+s390-pci-support-mmap-of-pci-resources-except-for-is.patch
+pci-msi-convert-pci_msi_ignore_mask-to-per-msi-domai.patch
+pci-msi-handle-the-nomask-flag-correctly-for-all-pci.patch
+pci-msi-add-an-option-to-write-msix-entry_data-befor.patch
+accel-ivpu-add-auto-selection-logic-for-job-schedule.patch
+accel-ivpu-fix-the-npu-s-dpu-frequency-calculation.patch
+ubsan-overflow-rework-integer-overflow-sanitizer-opt.patch
+lib-kconfig.ubsan-remove-default-ubsan-from-ubsan_in.patch
+ksmbd-use-__gfp_retry_mayfail.patch
+ksmbd-add-netdev-up-down-event-debug-print.patch
+ksmbd-browse-interfaces-list-on-fsctl_query_interfac.patch
+ksmbd-fix-use-after-free-in-__smb2_lease_break_noti.patch
+scsi-ufs-exynos-remove-empty-drv_init-method.patch
+scsi-ufs-exynos-remove-superfluous-function-paramete.patch
+scsi-ufs-exynos-add-gs101_ufs_drv_init-hook-and-enab.patch
+scsi-ufs-exynos-move-ufs-shareability-value-to-drvda.patch
+scsi-ufs-exynos-disable-iocc-if-dma-coherent-propert.patch
+net-niu-niu-requires-msix-entry_data-fields-touch-be.patch
+drm-xe-bmg-add-one-additional-pci-id.patch
+drm-amd-display-fix-unnecessary-cast-warnings-from-c.patch
+drm-amd-display-dml2-use-vzalloc-rather-than-kzalloc.patch
--- /dev/null
+From e78f99b06dd9642c03b98b653c82a5e4b48e4ff8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 17 Jan 2025 14:18:50 +0000
+Subject: soc: qcom: ice: introduce devm_of_qcom_ice_get
+
+From: Tudor Ambarus <tudor.ambarus@linaro.org>
+
+[ Upstream commit 1c13d6060d612601a61423f2e8fbf9e48126acca ]
+
+Callers of of_qcom_ice_get() leak the device reference taken by
+of_find_device_by_node(). Introduce devm variant for of_qcom_ice_get().
+Existing consumers need the ICE instance for the entire life of their
+device, thus exporting qcom_ice_put() is not required.
+
+Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20250117-qcom-ice-fix-dev-leak-v2-1-1ffa5b6884cb@linaro.org
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Stable-dep-of: cbef7442fba5 ("mmc: sdhci-msm: fix dev reference leaked through of_qcom_ice_get")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soc/qcom/ice.c | 48 ++++++++++++++++++++++++++++++++++++++++++
+ include/soc/qcom/ice.h | 2 ++
+ 2 files changed, 50 insertions(+)
+
+diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
+index 50be7a9274a14..9d89bfc50e8b8 100644
+--- a/drivers/soc/qcom/ice.c
++++ b/drivers/soc/qcom/ice.c
+@@ -11,6 +11,7 @@
+ #include <linux/cleanup.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/device.h>
+ #include <linux/iopoll.h>
+ #include <linux/of.h>
+ #include <linux/of_platform.h>
+@@ -324,6 +325,53 @@ struct qcom_ice *of_qcom_ice_get(struct device *dev)
+ }
+ EXPORT_SYMBOL_GPL(of_qcom_ice_get);
+
++static void qcom_ice_put(const struct qcom_ice *ice)
++{
++ struct platform_device *pdev = to_platform_device(ice->dev);
++
++ if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice"))
++ platform_device_put(pdev);
++}
++
++static void devm_of_qcom_ice_put(struct device *dev, void *res)
++{
++ qcom_ice_put(*(struct qcom_ice **)res);
++}
++
++/**
++ * devm_of_qcom_ice_get() - Devres managed helper to get an ICE instance from
++ * a DT node.
++ * @dev: device pointer for the consumer device.
++ *
++ * This function will provide an ICE instance either by creating one for the
++ * consumer device if its DT node provides the 'ice' reg range and the 'ice'
++ * clock (for legacy DT style). On the other hand, if consumer provides a
++ * phandle via 'qcom,ice' property to an ICE DT, the ICE instance will already
++ * be created and so this function will return that instead.
++ *
++ * Return: ICE pointer on success, NULL if there is no ICE data provided by the
++ * consumer or ERR_PTR() on error.
++ */
++struct qcom_ice *devm_of_qcom_ice_get(struct device *dev)
++{
++ struct qcom_ice *ice, **dr;
++
++ dr = devres_alloc(devm_of_qcom_ice_put, sizeof(*dr), GFP_KERNEL);
++ if (!dr)
++ return ERR_PTR(-ENOMEM);
++
++ ice = of_qcom_ice_get(dev);
++ if (!IS_ERR_OR_NULL(ice)) {
++ *dr = ice;
++ devres_add(dev, dr);
++ } else {
++ devres_free(dr);
++ }
++
++ return ice;
++}
++EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get);
++
+ static int qcom_ice_probe(struct platform_device *pdev)
+ {
+ struct qcom_ice *engine;
+diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h
+index 5870a94599a25..d5f6a228df659 100644
+--- a/include/soc/qcom/ice.h
++++ b/include/soc/qcom/ice.h
+@@ -34,4 +34,6 @@ int qcom_ice_program_key(struct qcom_ice *ice,
+ int slot);
+ int qcom_ice_evict_key(struct qcom_ice *ice, int slot);
+ struct qcom_ice *of_qcom_ice_get(struct device *dev);
++struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
++
+ #endif /* __QCOM_ICE_H__ */
+--
+2.39.5
+
--- /dev/null
+From 0ee78d76c3cccae22ab13826f9eeaa025acb72bb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Oct 2024 19:36:28 +0000
+Subject: tracing: Add __print_dynamic_array() helper
+
+From: Steven Rostedt <rostedt@goodmis.org>
+
+[ Upstream commit e52750fb1458ae9ea5860a08ed7a149185bc5b97 ]
+
+When printing a dynamic array in a trace event, the method is rather ugly.
+It has the format of:
+
+ __print_array(__get_dynamic_array(array),
+ __get_dynmaic_array_len(array) / el_size, el_size)
+
+Since dynamic arrays are known to the tracing infrastructure, create a
+helper macro that does the above for you.
+
+ __print_dynamic_array(array, el_size)
+
+Which would expand to the same output.
+
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
+Link: https://lore.kernel.org/r/20241022194158.110073-3-avadhut.naik@amd.com
+Stable-dep-of: ea8d7647f9dd ("tracing: Verify event formats that have "%*p.."")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/trace/stages/stage3_trace_output.h | 8 ++++++++
+ include/trace/stages/stage7_class_define.h | 1 +
+ samples/trace_events/trace-events-sample.h | 7 ++++++-
+ 3 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/include/trace/stages/stage3_trace_output.h b/include/trace/stages/stage3_trace_output.h
+index c1fb1355d3094..1e7b0bef95f52 100644
+--- a/include/trace/stages/stage3_trace_output.h
++++ b/include/trace/stages/stage3_trace_output.h
+@@ -119,6 +119,14 @@
+ trace_print_array_seq(p, array, count, el_size); \
+ })
+
++#undef __print_dynamic_array
++#define __print_dynamic_array(array, el_size) \
++ ({ \
++ __print_array(__get_dynamic_array(array), \
++ __get_dynamic_array_len(array) / (el_size), \
++ (el_size)); \
++ })
++
+ #undef __print_hex_dump
+ #define __print_hex_dump(prefix_str, prefix_type, \
+ rowsize, groupsize, buf, len, ascii) \
+diff --git a/include/trace/stages/stage7_class_define.h b/include/trace/stages/stage7_class_define.h
+index bcb960d16fc0e..fcd564a590f43 100644
+--- a/include/trace/stages/stage7_class_define.h
++++ b/include/trace/stages/stage7_class_define.h
+@@ -22,6 +22,7 @@
+ #undef __get_rel_cpumask
+ #undef __get_rel_sockaddr
+ #undef __print_array
++#undef __print_dynamic_array
+ #undef __print_hex_dump
+ #undef __get_buf
+
+diff --git a/samples/trace_events/trace-events-sample.h b/samples/trace_events/trace-events-sample.h
+index 55f9a3da92d5f..999f78d380aee 100644
+--- a/samples/trace_events/trace-events-sample.h
++++ b/samples/trace_events/trace-events-sample.h
+@@ -319,7 +319,7 @@ TRACE_EVENT(foo_bar,
+ __assign_cpumask(cpum, cpumask_bits(mask));
+ ),
+
+- TP_printk("foo %s %d %s %s %s %s %s (%s) (%s) %s", __entry->foo, __entry->bar,
++ TP_printk("foo %s %d %s %s %s %s %s %s (%s) (%s) %s", __entry->foo, __entry->bar,
+
+ /*
+ * Notice here the use of some helper functions. This includes:
+@@ -363,6 +363,11 @@ TRACE_EVENT(foo_bar,
+ __print_array(__get_dynamic_array(list),
+ __get_dynamic_array_len(list) / sizeof(int),
+ sizeof(int)),
++
++/* A shortcut is to use __print_dynamic_array for dynamic arrays */
++
++ __print_dynamic_array(list, sizeof(int)),
++
+ __get_str(str), __get_str(lstr),
+ __get_bitmask(cpus), __get_cpumask(cpum),
+ __get_str(vstr))
+--
+2.39.5
+
--- /dev/null
+From 7ad49357a09805e33d2bf4b6e8798333dbd2b0f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 27 Mar 2025 19:53:11 -0400
+Subject: tracing: Verify event formats that have "%*p.."
+
+From: Steven Rostedt <rostedt@goodmis.org>
+
+[ Upstream commit ea8d7647f9ddf1f81e2027ed305299797299aa03 ]
+
+The trace event verifier checks the formats of trace events to make sure
+that they do not point at memory that is not in the trace event itself or
+in data that will never be freed. If an event references data that was
+allocated when the event triggered and that same data is freed before the
+event is read, then the kernel can crash by reading freed memory.
+
+The verifier runs at boot up (or module load) and scans the print formats
+of the events and checks their arguments to make sure that dereferenced
+pointers are safe. If the format uses "%*p.." the verifier will ignore it,
+and that could be dangerous. Cover this case as well.
+
+Also add to the sample code a use case of "%*pbl".
+
+Link: https://lore.kernel.org/all/bcba4d76-2c3f-4d11-baf0-02905db953dd@oracle.com/
+
+Cc: stable@vger.kernel.org
+Cc: Masami Hiramatsu <mhiramat@kernel.org>
+Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
+Fixes: 5013f454a352c ("tracing: Add check of trace event print fmts for dereferencing pointers")
+Link: https://lore.kernel.org/20250327195311.2d89ec66@gandalf.local.home
+Reported-by: Libo Chen <libo.chen@oracle.com>
+Reviewed-by: Libo Chen <libo.chen@oracle.com>
+Tested-by: Libo Chen <libo.chen@oracle.com>
+Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/trace/trace_events.c | 7 +++++++
+ samples/trace_events/trace-events-sample.h | 8 ++++++--
+ 2 files changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
+index 11dea25ef880a..15fb255733fb6 100644
+--- a/kernel/trace/trace_events.c
++++ b/kernel/trace/trace_events.c
+@@ -470,6 +470,7 @@ static void test_event_printk(struct trace_event_call *call)
+ case '%':
+ continue;
+ case 'p':
++ do_pointer:
+ /* Find dereferencing fields */
+ switch (fmt[i + 1]) {
+ case 'B': case 'R': case 'r':
+@@ -498,6 +499,12 @@ static void test_event_printk(struct trace_event_call *call)
+ continue;
+ if (fmt[i + j] == '*') {
+ star = true;
++ /* Handle %*pbl case */
++ if (!j && fmt[i + 1] == 'p') {
++ arg++;
++ i++;
++ goto do_pointer;
++ }
+ continue;
+ }
+ if ((fmt[i + j] == 's')) {
+diff --git a/samples/trace_events/trace-events-sample.h b/samples/trace_events/trace-events-sample.h
+index 999f78d380aee..1a05fc1533531 100644
+--- a/samples/trace_events/trace-events-sample.h
++++ b/samples/trace_events/trace-events-sample.h
+@@ -319,7 +319,8 @@ TRACE_EVENT(foo_bar,
+ __assign_cpumask(cpum, cpumask_bits(mask));
+ ),
+
+- TP_printk("foo %s %d %s %s %s %s %s %s (%s) (%s) %s", __entry->foo, __entry->bar,
++ TP_printk("foo %s %d %s %s %s %s %s %s (%s) (%s) %s [%d] %*pbl",
++ __entry->foo, __entry->bar,
+
+ /*
+ * Notice here the use of some helper functions. This includes:
+@@ -370,7 +371,10 @@ TRACE_EVENT(foo_bar,
+
+ __get_str(str), __get_str(lstr),
+ __get_bitmask(cpus), __get_cpumask(cpum),
+- __get_str(vstr))
++ __get_str(vstr),
++ __get_dynamic_array_len(cpus),
++ __get_dynamic_array_len(cpus),
++ __get_dynamic_array(cpus))
+ );
+
+ /*
+--
+2.39.5
+
--- /dev/null
+From a2f4dba8299abd79ef254d28b56299b84ef57be3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Mar 2025 20:19:09 -0800
+Subject: ubsan/overflow: Rework integer overflow sanitizer option to turn on
+ everything
+
+From: Kees Cook <kees@kernel.org>
+
+[ Upstream commit ed2b548f1017586c44f50654ef9febb42d491f31 ]
+
+Since we're going to approach integer overflow mitigation a type at a
+time, we need to enable all of the associated sanitizers, and then opt
+into types one at a time.
+
+Rename the existing "signed wrap" sanitizer to just the entire topic area:
+"integer wrap". Enable the implicit integer truncation sanitizers, with
+required callbacks and tests.
+
+Notably, this requires features (currently) only available in Clang,
+so we can depend on the cc-option tests to determine availability
+instead of doing version tests.
+
+Link: https://lore.kernel.org/r/20250307041914.937329-1-kees@kernel.org
+Signed-off-by: Kees Cook <kees@kernel.org>
+Stable-dep-of: cdc2e1d9d929 ("lib/Kconfig.ubsan: Remove 'default UBSAN' from UBSAN_INTEGER_WRAP")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/compiler_types.h | 2 +-
+ kernel/configs/hardening.config | 2 +-
+ lib/Kconfig.ubsan | 23 +++++++++++------------
+ lib/test_ubsan.c | 18 ++++++++++++++----
+ lib/ubsan.c | 28 ++++++++++++++++++++++++++--
+ lib/ubsan.h | 8 ++++++++
+ scripts/Makefile.lib | 4 ++--
+ scripts/Makefile.ubsan | 8 ++++++--
+ 8 files changed, 69 insertions(+), 24 deletions(-)
+
+diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
+index 639be0f30b455..7a98ea0bc34ed 100644
+--- a/include/linux/compiler_types.h
++++ b/include/linux/compiler_types.h
+@@ -354,7 +354,7 @@ struct ftrace_likely_data {
+ #endif
+
+ /* Do not trap wrapping arithmetic within an annotated function. */
+-#ifdef CONFIG_UBSAN_SIGNED_WRAP
++#ifdef CONFIG_UBSAN_INTEGER_WRAP
+ # define __signed_wrap __attribute__((no_sanitize("signed-integer-overflow")))
+ #else
+ # define __signed_wrap
+diff --git a/kernel/configs/hardening.config b/kernel/configs/hardening.config
+index 3fabb8f55ef6e..dd7c32fb5ac1b 100644
+--- a/kernel/configs/hardening.config
++++ b/kernel/configs/hardening.config
+@@ -46,7 +46,7 @@ CONFIG_UBSAN_BOUNDS=y
+ # CONFIG_UBSAN_SHIFT is not set
+ # CONFIG_UBSAN_DIV_ZERO is not set
+ # CONFIG_UBSAN_UNREACHABLE is not set
+-# CONFIG_UBSAN_SIGNED_WRAP is not set
++# CONFIG_UBSAN_INTEGER_WRAP is not set
+ # CONFIG_UBSAN_BOOL is not set
+ # CONFIG_UBSAN_ENUM is not set
+ # CONFIG_UBSAN_ALIGNMENT is not set
+diff --git a/lib/Kconfig.ubsan b/lib/Kconfig.ubsan
+index 1d4aa7a83b3a5..63e5622010e0f 100644
+--- a/lib/Kconfig.ubsan
++++ b/lib/Kconfig.ubsan
+@@ -116,21 +116,20 @@ config UBSAN_UNREACHABLE
+ This option enables -fsanitize=unreachable which checks for control
+ flow reaching an expected-to-be-unreachable position.
+
+-config UBSAN_SIGNED_WRAP
+- bool "Perform checking for signed arithmetic wrap-around"
++config UBSAN_INTEGER_WRAP
++ bool "Perform checking for integer arithmetic wrap-around"
+ default UBSAN
+ depends on !COMPILE_TEST
+- # The no_sanitize attribute was introduced in GCC with version 8.
+- depends on !CC_IS_GCC || GCC_VERSION >= 80000
+ depends on $(cc-option,-fsanitize=signed-integer-overflow)
+- help
+- This option enables -fsanitize=signed-integer-overflow which checks
+- for wrap-around of any arithmetic operations with signed integers.
+- This currently performs nearly no instrumentation due to the
+- kernel's use of -fno-strict-overflow which converts all would-be
+- arithmetic undefined behavior into wrap-around arithmetic. Future
+- sanitizer versions will allow for wrap-around checking (rather than
+- exclusively undefined behavior).
++ depends on $(cc-option,-fsanitize=unsigned-integer-overflow)
++ depends on $(cc-option,-fsanitize=implicit-signed-integer-truncation)
++ depends on $(cc-option,-fsanitize=implicit-unsigned-integer-truncation)
++ help
++ This option enables all of the sanitizers involved in integer overflow
++ (wrap-around) mitigation: signed-integer-overflow, unsigned-integer-overflow,
++ implicit-signed-integer-truncation, and implicit-unsigned-integer-truncation.
++ This is currently limited only to the size_t type while testing and
++ compiler development continues.
+
+ config UBSAN_BOOL
+ bool "Perform checking for non-boolean values used as boolean"
+diff --git a/lib/test_ubsan.c b/lib/test_ubsan.c
+index 5d7b10e986107..8772e5edaa4fa 100644
+--- a/lib/test_ubsan.c
++++ b/lib/test_ubsan.c
+@@ -15,7 +15,7 @@ static void test_ubsan_add_overflow(void)
+ {
+ volatile int val = INT_MAX;
+
+- UBSAN_TEST(CONFIG_UBSAN_SIGNED_WRAP);
++ UBSAN_TEST(CONFIG_UBSAN_INTEGER_WRAP);
+ val += 2;
+ }
+
+@@ -24,7 +24,7 @@ static void test_ubsan_sub_overflow(void)
+ volatile int val = INT_MIN;
+ volatile int val2 = 2;
+
+- UBSAN_TEST(CONFIG_UBSAN_SIGNED_WRAP);
++ UBSAN_TEST(CONFIG_UBSAN_INTEGER_WRAP);
+ val -= val2;
+ }
+
+@@ -32,7 +32,7 @@ static void test_ubsan_mul_overflow(void)
+ {
+ volatile int val = INT_MAX / 2;
+
+- UBSAN_TEST(CONFIG_UBSAN_SIGNED_WRAP);
++ UBSAN_TEST(CONFIG_UBSAN_INTEGER_WRAP);
+ val *= 3;
+ }
+
+@@ -40,7 +40,7 @@ static void test_ubsan_negate_overflow(void)
+ {
+ volatile int val = INT_MIN;
+
+- UBSAN_TEST(CONFIG_UBSAN_SIGNED_WRAP);
++ UBSAN_TEST(CONFIG_UBSAN_INTEGER_WRAP);
+ val = -val;
+ }
+
+@@ -53,6 +53,15 @@ static void test_ubsan_divrem_overflow(void)
+ val /= val2;
+ }
+
++static void test_ubsan_truncate_signed(void)
++{
++ volatile long val = LONG_MAX;
++ volatile int val2 = 0;
++
++ UBSAN_TEST(CONFIG_UBSAN_INTEGER_WRAP);
++ val2 = val;
++}
++
+ static void test_ubsan_shift_out_of_bounds(void)
+ {
+ volatile int neg = -1, wrap = 4;
+@@ -127,6 +136,7 @@ static const test_ubsan_fp test_ubsan_array[] = {
+ test_ubsan_sub_overflow,
+ test_ubsan_mul_overflow,
+ test_ubsan_negate_overflow,
++ test_ubsan_truncate_signed,
+ test_ubsan_shift_out_of_bounds,
+ test_ubsan_out_of_bounds,
+ test_ubsan_load_invalid_value,
+diff --git a/lib/ubsan.c b/lib/ubsan.c
+index a1c983d148f16..cdc1d31c3821b 100644
+--- a/lib/ubsan.c
++++ b/lib/ubsan.c
+@@ -44,7 +44,7 @@ const char *report_ubsan_failure(struct pt_regs *regs, u32 check_type)
+ case ubsan_shift_out_of_bounds:
+ return "UBSAN: shift out of bounds";
+ #endif
+-#if defined(CONFIG_UBSAN_DIV_ZERO) || defined(CONFIG_UBSAN_SIGNED_WRAP)
++#if defined(CONFIG_UBSAN_DIV_ZERO) || defined(CONFIG_UBSAN_INTEGER_WRAP)
+ /*
+ * SanitizerKind::IntegerDivideByZero and
+ * SanitizerKind::SignedIntegerOverflow emit
+@@ -79,7 +79,7 @@ const char *report_ubsan_failure(struct pt_regs *regs, u32 check_type)
+ case ubsan_type_mismatch:
+ return "UBSAN: type mismatch";
+ #endif
+-#ifdef CONFIG_UBSAN_SIGNED_WRAP
++#ifdef CONFIG_UBSAN_INTEGER_WRAP
+ /*
+ * SanitizerKind::SignedIntegerOverflow emits
+ * SanitizerHandler::AddOverflow, SanitizerHandler::SubOverflow,
+@@ -303,6 +303,30 @@ void __ubsan_handle_negate_overflow(void *_data, void *old_val)
+ }
+ EXPORT_SYMBOL(__ubsan_handle_negate_overflow);
+
++void __ubsan_handle_implicit_conversion(void *_data, void *from_val, void *to_val)
++{
++ struct implicit_conversion_data *data = _data;
++ char from_val_str[VALUE_LENGTH];
++ char to_val_str[VALUE_LENGTH];
++
++ if (suppress_report(&data->location))
++ return;
++
++ val_to_string(from_val_str, sizeof(from_val_str), data->from_type, from_val);
++ val_to_string(to_val_str, sizeof(to_val_str), data->to_type, to_val);
++
++ ubsan_prologue(&data->location, "implicit-conversion");
++
++ pr_err("cannot represent %s value %s during %s %s, truncated to %s\n",
++ data->from_type->type_name,
++ from_val_str,
++ type_check_kinds[data->type_check_kind],
++ data->to_type->type_name,
++ to_val_str);
++
++ ubsan_epilogue();
++}
++EXPORT_SYMBOL(__ubsan_handle_implicit_conversion);
+
+ void __ubsan_handle_divrem_overflow(void *_data, void *lhs, void *rhs)
+ {
+diff --git a/lib/ubsan.h b/lib/ubsan.h
+index 07e37d4429b4b..b37e22374e774 100644
+--- a/lib/ubsan.h
++++ b/lib/ubsan.h
+@@ -62,6 +62,13 @@ struct overflow_data {
+ struct type_descriptor *type;
+ };
+
++struct implicit_conversion_data {
++ struct source_location location;
++ struct type_descriptor *from_type;
++ struct type_descriptor *to_type;
++ unsigned char type_check_kind;
++};
++
+ struct type_mismatch_data {
+ struct source_location location;
+ struct type_descriptor *type;
+@@ -142,6 +149,7 @@ void ubsan_linkage __ubsan_handle_sub_overflow(void *data, void *lhs, void *rhs)
+ void ubsan_linkage __ubsan_handle_mul_overflow(void *data, void *lhs, void *rhs);
+ void ubsan_linkage __ubsan_handle_negate_overflow(void *_data, void *old_val);
+ void ubsan_linkage __ubsan_handle_divrem_overflow(void *_data, void *lhs, void *rhs);
++void ubsan_linkage __ubsan_handle_implicit_conversion(void *_data, void *lhs, void *rhs);
+ void ubsan_linkage __ubsan_handle_type_mismatch(struct type_mismatch_data *data, void *ptr);
+ void ubsan_linkage __ubsan_handle_type_mismatch_v1(void *_data, void *ptr);
+ void ubsan_linkage __ubsan_handle_out_of_bounds(void *_data, void *index);
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index fe5e132fcea89..43bdbb5dd43ea 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -166,8 +166,8 @@ _c_flags += $(if $(patsubst n%,, \
+ $(UBSAN_SANITIZE_$(target-stem).o)$(UBSAN_SANITIZE)$(is-kernel-object)), \
+ $(CFLAGS_UBSAN))
+ _c_flags += $(if $(patsubst n%,, \
+- $(UBSAN_SIGNED_WRAP_$(target-stem).o)$(UBSAN_SANITIZE_$(target-stem).o)$(UBSAN_SIGNED_WRAP)$(UBSAN_SANITIZE)$(is-kernel-object)), \
+- $(CFLAGS_UBSAN_SIGNED_WRAP))
++ $(UBSAN_INTEGER_WRAP_$(target-stem).o)$(UBSAN_SANITIZE_$(target-stem).o)$(UBSAN_INTEGER_WRAP)$(UBSAN_SANITIZE)$(is-kernel-object)), \
++ $(CFLAGS_UBSAN_INTEGER_WRAP))
+ endif
+
+ ifeq ($(CONFIG_KCOV),y)
+diff --git a/scripts/Makefile.ubsan b/scripts/Makefile.ubsan
+index b2d3b273b8028..4fad9afed24cf 100644
+--- a/scripts/Makefile.ubsan
++++ b/scripts/Makefile.ubsan
+@@ -14,5 +14,9 @@ ubsan-cflags-$(CONFIG_UBSAN_TRAP) += $(call cc-option,-fsanitize-trap=undefined
+
+ export CFLAGS_UBSAN := $(ubsan-cflags-y)
+
+-ubsan-signed-wrap-cflags-$(CONFIG_UBSAN_SIGNED_WRAP) += -fsanitize=signed-integer-overflow
+-export CFLAGS_UBSAN_SIGNED_WRAP := $(ubsan-signed-wrap-cflags-y)
++ubsan-integer-wrap-cflags-$(CONFIG_UBSAN_INTEGER_WRAP) += \
++ -fsanitize=signed-integer-overflow \
++ -fsanitize=unsigned-integer-overflow \
++ -fsanitize=implicit-signed-integer-truncation \
++ -fsanitize=implicit-unsigned-integer-truncation
++export CFLAGS_UBSAN_INTEGER_WRAP := $(ubsan-integer-wrap-cflags-y)
+--
+2.39.5
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
