arm64: dts: qcom: sc7280: Remove CTS/RTS configuration

[ Upstream commit 2b96407b8f10f1d71b58cb35704eb91b8ea78db1 ]

For IDP variant, GPIO 20/21 is used by camera use case and camera
driver is not able acquire these GPIOs as it is acquired by UART5
driver as RTS/CTS pin.

UART5 is designed for debug UART for all the board variants of the
sc7280 chipset and RTS/CTS configuration is not required for debug
uart usecase.

Remove CTS/RTS configuration for UART5 instance and change compatible
string to debug UART.

Remove overwriting compatible property from individual target specific
file as it is not required.

Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node")
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20240424075853.11445-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index f3432701945f7f35713e05945a6b116ea85ceef6..8cd2fe80dbb2cab5b0ffce03cec5a2d87a8a794b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -864,7 +864,6 @@
 };
 
 &uart5 {
-       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
index 47ca2d000341418d4b5757570dc3ed67ccf1e239..107302680f56240ba6ad2e8e49272db254aa75fe 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts
@@ -658,7 +658,6 @@
 };
 
 &uart5 {
-       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index a085ff5b5fb21d9cc68c8dd970f30d489a40894b..7256b51eb08f9f8c3f9498ea22b957768d349daa 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -632,7 +632,6 @@
 };
 
 &uart5 {
-       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index a0059527d9e48a45e542010143740019cd612d44..7370aa0dbf0e3f9e7a3e38c3f00686e1d3dcbc9f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -495,7 +495,6 @@
 };
 
 &uart5 {
-       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index f9b96bd2477ea60f94372924dd8823b5198ded65..7d1d5bbbbbd951345f54fb3181ee18821d2b9158 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -427,7 +427,6 @@
 };
 
 uart_dbg: &uart5 {
-       compatible = "qcom,geni-debug-uart";
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2f7780f629ac576661210e8878149691711e4d10..c4a05d7b7ce65c9eebe035d969c24865c6ed8823 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1440,12 +1440,12 @@
                        };
 
                        uart5: serial@994000 {
-                               compatible = "qcom,geni-uart";
+                               compatible = "qcom,geni-debug-uart";
                                reg = <0 0x00994000 0 0x4000>;
                                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                                clock-names = "se";
                                pinctrl-names = "default";
-                               pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
+                               pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
                                interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
                                power-domains = <&rpmhpd SC7280_CX>;
                                operating-points-v2 = <&qup_opp_table>;
@@ -5408,16 +5408,6 @@
                                function = "qup04";
                        };
 
-                       qup_uart5_cts: qup-uart5-cts-state {
-                               pins = "gpio20";
-                               function = "qup05";
-                       };
-
-                       qup_uart5_rts: qup-uart5-rts-state {
-                               pins = "gpio21";
-                               function = "qup05";
-                       };
-
                        qup_uart5_tx: qup-uart5-tx-state {
                                pins = "gpio22";
                                function = "qup05";