drm/xe: Load HuC on Alderlake P

Alderlake P uses TGL HuC and it was not added together with ADL-S,
because it was failing for unrelated reasons. Now that those are fixed,
allow it to load HuC.

	# cat /sys/kernel/debug/dri/0/gt0/uc/huc_info
	HuC firmware: i915/tgl_huc.bin
		status: RUNNING
		version: wanted 0.0, found 7.9
		uCode: 589504 bytes
		RSA: 256 bytes

	HuC status: 0x00090001

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://lore.kernel.org/r/20230512233649.3218736-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 609ca3f2ffa4bb1030da56310b03a7325853fc71..5703213bdf1b5c9afd97866be3dd8658270fa87f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -111,6 +111,7 @@ struct fw_blobs_by_type {
        fw_def(TIGERLAKE,       major_ver(i915, guc,    tgl,    70, 5))
 
 #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver)                          \
+       fw_def(ALDERLAKE_P,     no_ver(i915,    huc,    tgl))                   \
        fw_def(ALDERLAKE_S,     no_ver(i915,    huc,    tgl))                   \
        fw_def(DG1,             no_ver(i915,    huc,    dg1))                   \
        fw_def(ROCKETLAKE,      no_ver(i915,    huc,    tgl))                   \