arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP

The ISP HDR stitching registers are clocked by the pixel clock, which is
gated by the MIPI_CSI2 power domain. Attempting to access those
registers with the clock off locks up the system. Fix this by adding the
pclk clock and the MIPI_CSI2 secondary power domain.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb24dba7338ea00dd50c5f7e409d72ecb7d790b9..5d10de3950c3488acc80f574c8c59b55b6fbf575 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1701,9 +1701,12 @@
                                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
                                         <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
-                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
-                               clock-names = "isp", "aclk", "hclk";
-                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
+                               clock-names = "isp", "aclk", "hclk", "pclk";
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
+                                               <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+                               power-domain-names = "isp", "csi2";
                                fsl,blk-ctrl = <&media_blk_ctrl 0>;
                                status = "disabled";
 
@@ -1723,9 +1726,12 @@
                                interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
                                         <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
-                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
-                               clock-names = "isp", "aclk", "hclk";
-                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+                                        <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                                        <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
+                               clock-names = "isp", "aclk", "hclk", "pclk";
+                               power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
+                                               <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+                               power-domain-names = "isp", "csi2";
                                fsl,blk-ctrl = <&media_blk_ctrl 1>;
                                status = "disabled";