pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, val, err);
}
-#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE)
+#define KVM_SUPPORTED_TD_ATTRS (TDX_ATTR_SEPT_VE_DISABLE)
static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm)
{
vcpu->arch.l1_tsc_scaling_ratio = kvm_tdx->tsc_multiplier;
vcpu->arch.guest_state_protected =
- !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_TD_ATTR_DEBUG);
+ !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_ATTR_DEBUG);
if ((kvm_tdx->xfam & XFEATURE_MASK_XTILE) == XFEATURE_MASK_XTILE)
vcpu->arch.xfd_no_write_intercept = true;
u32 edx;
} __packed;
-#define TDX_TD_ATTR_DEBUG BIT_ULL(0)
-#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(28)
-#define TDX_TD_ATTR_PKS BIT_ULL(30)
-#define TDX_TD_ATTR_KL BIT_ULL(31)
-#define TDX_TD_ATTR_PERFMON BIT_ULL(63)
-
#define TDX_EXT_EXIT_QUAL_TYPE_MASK GENMASK(3, 0)
#define TDX_EXT_EXIT_QUAL_TYPE_PENDING_EPT_VIOLATION 6
/*