x86/resctrl: Remove hard-coded memory bandwidth limit

[ Upstream commit 0976783bb123f30981bc1e7a14d9626a6f63aeac ]

The QOS Memory Bandwidth Enforcement Limit is reported by
CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02:

  Bits	 Description
  31:0	 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit.

Newer processors can support higher bandwidth limit than the current
hard-coded value. Remove latter and detect using CPUID instead. Also,
update the register variables eax and edx to match the AMD CPUID
definition.

The CPUID details are documented in the Processor Programming Reference
(PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25 in the
Link tag below.

Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Link: https://lore.kernel.org/r/c26a8ca79d399ed076cf8bf2e9fbc58048808289.1705359148.git.babu.moger@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 19e0681f04356d6b184014003e23cc5cec3980f6..d04371e851b4c21a0044883336496df1189bcc96 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource *r)
 static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
 {
        struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
-       union cpuid_0x10_3_eax eax;
-       union cpuid_0x10_x_edx edx;
-       u32 ebx, ecx, subleaf;
+       u32 eax, ebx, ecx, edx, subleaf;
 
        /*
         * Query CPUID_Fn80000020_EDX_x01 for MBA and
@@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
         */
        subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 :  1;
 
-       cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full);
-       hw_res->num_closid = edx.split.cos_max + 1;
-       r->default_ctrl = MAX_MBA_BW_AMD;
+       cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx);
+       hw_res->num_closid = edx + 1;
+       r->default_ctrl = 1 << eax;
 
        /* AMD does not use delay */
        r->membw.delay_linear = false;

diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index a4f1aa15f0a2a8d38de404aa4cb539359f3bbe8c..d2979748fae47ae1c4c8205707eb0b083040ebc8 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -18,7 +18,6 @@
 #define MBM_OVERFLOW_INTERVAL          1000
 #define MAX_MBA_BW                     100u
 #define MBA_IS_LINEAR                  0x4
-#define MAX_MBA_BW_AMD                 0x800
 #define MBM_CNTR_WIDTH_OFFSET_AMD      20
 
 #define RMID_VAL_ERROR                 BIT_ULL(63)