The QSPI frequency set by the ROM may not be using the 1/2 clock divider,
examining the
E000D000 register at boot reveils it's usually set to 1/4.
The driver always assumes it is set at 1/2 at boot, so it does not program
the clock rate if the requested frequency happens to match that.
This results in the QSPI clock running at 50MHz when 100MHz was requested.
To fix, set the current rate of the master (speed_hz) to "0" at startup, so
that the driver always programs the clock divider the first time the
zynq_qspi_setup_transfer method is called. This assures that the QSPI is
actually running at the requested clock rate.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mike Looijmans <mike.looijmans@topic.nl>
qspi->slave.dio = is_dio;
qspi->slave.op_mode_rx = SPI_OPM_RX_QOF;
qspi->slave.op_mode_tx = SPI_OPM_TX_QPP;
- qspi->qspi.master.speed_hz = qspi->qspi.master.input_clk_hz / 2;
- qspi->qspi.max_speed_hz = (max_hz < qspi->qspi.master.speed_hz) ?
- max_hz : qspi->qspi.master.speed_hz;
+ lqspi_frequency = qspi->qspi.master.input_clk_hz / 2;
+ qspi->qspi.max_speed_hz = min(max_hz, lqspi_frequency);
qspi->qspi.master.is_dio = is_dio;
qspi->qspi.master.is_dual = is_dual;
qspi->qspi.mode = mode;