perf/x86/intel/ds: Factor out PEBS record processing code to functions

Beside some PEBS record layout difference, arch-PEBS can share most of
PEBS record processing code with adaptive PEBS. Thus, factor out these
common processing code to independent inline functions, so they can be
reused by subsequent arch-PEBS handler.

Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20251029102136.61364-7-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 26e485eca0a05f5e23c74b607158fdefe25395c0..c8aa72db86d92d406733838f7f4471de984fd3f6 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2614,6 +2614,57 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
        }
 }
 
+static __always_inline void
+__intel_pmu_handle_pebs_record(struct pt_regs *iregs,
+                              struct pt_regs *regs,
+                              struct perf_sample_data *data,
+                              void *at, u64 pebs_status,
+                              short *counts, void **last,
+                              setup_fn setup_sample)
+{
+       struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+       struct perf_event *event;
+       int bit;
+
+       for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
+               event = cpuc->events[bit];
+
+               if (WARN_ON_ONCE(!event) ||
+                   WARN_ON_ONCE(!event->attr.precise_ip))
+                       continue;
+
+               if (counts[bit]++) {
+                       __intel_pmu_pebs_event(event, iregs, regs, data,
+                                              last[bit], setup_sample);
+               }
+
+               last[bit] = at;
+       }
+}
+
+static __always_inline void
+__intel_pmu_handle_last_pebs_record(struct pt_regs *iregs,
+                                   struct pt_regs *regs,
+                                   struct perf_sample_data *data,
+                                   u64 mask, short *counts, void **last,
+                                   setup_fn setup_sample)
+{
+       struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+       struct perf_event *event;
+       int bit;
+
+       for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
+               if (!counts[bit])
+                       continue;
+
+               event = cpuc->events[bit];
+
+               __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
+                                           counts[bit], setup_sample);
+       }
+
+}
+
 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
 {
        short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
@@ -2623,9 +2674,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
        struct x86_perf_regs perf_regs;
        struct pt_regs *regs = &perf_regs.regs;
        struct pebs_basic *basic;
-       struct perf_event *event;
        void *base, *at, *top;
-       int bit;
        u64 mask;
 
        if (!x86_pmu.pebs_active)
@@ -2638,6 +2687,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
 
        mask = hybrid(cpuc->pmu, pebs_events_mask) |
               (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);
+       mask &= cpuc->pebs_enabled;
 
        if (unlikely(base >= top)) {
                intel_pmu_pebs_event_update_no_drain(cpuc, mask);
@@ -2655,31 +2705,14 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
                if (basic->format_size != cpuc->pebs_record_size)
                        continue;
 
-               pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
-               for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
-                       event = cpuc->events[bit];
-
-                       if (WARN_ON_ONCE(!event) ||
-                           WARN_ON_ONCE(!event->attr.precise_ip))
-                               continue;
-
-                       if (counts[bit]++) {
-                               __intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
-                                                      setup_pebs_adaptive_sample_data);
-                       }
-                       last[bit] = at;
-               }
+               pebs_status = mask & basic->applicable_counters;
+               __intel_pmu_handle_pebs_record(iregs, regs, data, at,
+                                              pebs_status, counts, last,
+                                              setup_pebs_adaptive_sample_data);
        }
 
-       for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
-               if (!counts[bit])
-                       continue;
-
-               event = cpuc->events[bit];
-
-               __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
-                                           counts[bit], setup_pebs_adaptive_sample_data);
-       }
+       __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, counts, last,
+                                           setup_pebs_adaptive_sample_data);
 }
 
 static void __init intel_arch_pebs_init(void)