config TARGET_ZYNQMP_MINI
bool "ZynqMP MINI"
+config TARGET_ZYNQMP_ZC1751_XM015_DC1
+ bool "ZynqMP ZC1751 XM015 DC1"
+
+config TARGET_ZYNQMP_ZC1751_XM016_DC2
+ bool "ZynqMP ZC1751 XM016 DC2"
+
endchoice
config SYS_BOARD
config SYS_CONFIG_NAME
default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
default "xilinx_zynqmp_mini" if TARGET_ZYNQMP_MINI
+ default "xilinx_zynqmp_zc1751_xm015_dc1" if TARGET_ZYNQMP_ZC1751_XM015_DC1
+ default "xilinx_zynqmp_zc1751_xm016_dc2" if TARGET_ZYNQMP_ZC1751_XM016_DC2
config SECURE_IOU
bool "Configure ZynqMP secure IOU"
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
-dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb \
+ zynqmp-zc1751-xm015-dc1.dtb \
+ zynqmp-zc1751-xm016-dc2.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x80000000>, <0x8 0x00000000 0x80000000>; /* 4GB DIMM modules where 2GB are below 4GB (DDR_LOW) and the rest at DDR_HIGH */
+ /* PL address space - also with PL DDR 512MB-3GB, 16GB-24GB */
+ };
+ /* FIXME - there is also PL DDR - based on presentation 64GB */
+};
+
+&amba {
+ /* clock for uart, can, nand, i2c */
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ /* Gems */
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ /* clock for sd/emmc */
+ clk200: clk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ /* clock for usb */
+ clk250: clk250 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ /* clock for qspi */
+ clk300: clk300 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000000>;
+ };
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+ xlnx,overfetch; /* for testing purpose */
+ xlnx,ratectrl = <0>; /* for testing purpose */
+ xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+ xlnx,ratectrl = <100>; /* for testing purpose */
+ xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+ status = "okay";
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+ local-mac-address = [00 0a 35 00 02 90];
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>; /* FIXME not quite sure about this one */
+ /* max-speed = <100>; */ /* FIXME here for sure */
+ };
+};
+
+&gpio {
+ status = "okay";
+ clocks = <&clk100>; /* FIXME - can't find in the table */
+};
+
+/*
+&gpu {
+ status = "okay";
+};
+*/
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ clocks = <&clk100>;
+ eeprom@54 {
+ compatible = "at,24c64"; /* 24AA64 */
+ reg = <0x54>;
+ };
+/* This eeprom is connected on FMC to be detactable from SW point of view
+ address depends on FMC connector where it is plugged
+ eeprom@52 {
+ compatible = "at,24c02";
+ reg = <0x50>; // FIXME 0b10100xx
+ };
+*/
+};
+
+&qspi {
+ status = "okay";
+ clocks = <&clk300 &clk300>;
+ flash@0 {
+ compatible = "n25q512a11"; /* Micron MT25QU512ABB8ESF */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ clocks = <&clk250>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ clocks = <&clk200>, <&clk200>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ clocks = <&clk200>, <&clk200>;
+};
+
+&uart0 {
+ status = "okay";
+ clocks = <&clk100 &clk100>;
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ clocks = <&clk250>, <&clk250>;
+};
--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+/ {
+ model = "ZynqMP zc1751-xm016-dc2 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem2;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x80000000>, <0x8 0x00000000 0x80000000>; /* 4GB DIMM modules where 2GB are below 4GB (DDR_LOW) and the rest at DDR_HIGH */
+ /* PL address space - also with PL DDR 2GB-3GB, 16GB-24GB */
+ };
+ /* FIXME - there is also PL DDR - based on presentation 64GB */
+};
+
+&amba {
+ /* clock for uart, can, nand, i2c */
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ /* Gems */
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ /* clock for sd/emmc */
+ clk200: clk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ /* clock for usb */
+ clk250: clk250 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ /* clock for qspi */
+ clk300: clk300 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+ clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+ status = "okay";
+ clocks = <&clk100 &clk100>;
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+ xlnx,overfetch; /* for testing purpose */
+ xlnx,ratectrl = <0>; /* for testing purpose */
+ xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+ xlnx,ratectrl = <100>; /* for testing purpose */
+ xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&gem2 {
+ status = "okay";
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+ local-mac-address = [00 0a 35 00 02 90];
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{ /* DP83867 http://www.ti.com/lit/ds/symlink/dp83867ir.pdf ID 0x2000a231 */
+ reg = <0>; /* FIXME not quite sure about this one */
+ /* max-speed = <100>; */ /* FIXME here for sure */
+ ti,rx-internal-delay = <0x8>; /* FIXME DP83867_RGMIIDCTL_2_25_NS */
+ ti,tx-internal-delay = <0xa>; /* FIXME DP83867_RGMIIDCTL_2_75_NS */
+ ti,fifo-depth = <0x1>; /* default setup DP83867_PHYCR_FIFO_DEPTH_4_B_NIB */
+ };
+};
+
+&gpio {
+ status = "okay";
+ clocks = <&clk100>; /* FIXME - can't find in the table */
+};
+
+/*
+&gpu {
+ status = "okay";
+};
+*/
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ clocks = <&clk100>;
+
+ rtc@68 { /* FIXME address */
+ compatible = "dallas,ds1339"; /* http://datasheets.maximintegrated.com/en/ds/DS1339-DS1339U.pdf */
+ reg = <0x68>;
+ };
+
+
+/* This eeprom is connected on FMC to be detactable from SW point of view
+ address depends on FMC connector where it is plugged
+ eeprom@52 {
+ compatible = "at,24c02";
+ reg = <0x50>; // FIXME 0b10100xx
+ };
+
+ sw1@20 { // FMC address unknown
+ compatible = "nxp,pca9534"; // 8 gpios configurated as input
+ reg = <0x20>; // FIXME
+ };
+
+
+*/
+};
+
+&nand0 { /* CLK 100, Micron SLC family device MT29F32G08ABCDB - 2 cs - flashes in parralel */
+ status = "okay";
+ arasan,has-mdma;
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x1C00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x3000000 0x400000>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+ clocks = <&clk200 &clk200>;
+ spi0_flash0: spi0_flash0@0 {
+ compatible = "m25p80"; /* FIXME SST25WF080 */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi0_flash0@00000000 {
+ label = "spi0_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+ clocks = <&clk200 &clk200>;
+ spi1_flash0: spi1_flash0@0 {
+ compatible = "m25p80"; /* AT45DB041E 4Mbit */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <85000000>; /* Adesto datasheet http://www.adestotech.com/wp-content/uploads/doc8783.pdf */
+ reg = <0>;
+
+ spi1_flash0@00000000 {
+ label = "spi1_flash0";
+ reg = <0x0 0x400000>;
+ };
+ };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ clocks = <&clk250>, <&clk250>;
+};
+
+&uart0 {
+ status = "okay";
+ clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+ status = "okay";
+ clocks = <&clk100 &clk100>;
+};
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TARGET_ZYNQMP_ZC1751_XM015_DC1=y
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TARGET_ZYNQMP_ZC1751_XM015_DC1=y
+CONFIG_SECURE_IOU=y
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TARGET_ZYNQMP_ZC1751_XM016_DC2=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_ZYNQ_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TARGET_ZYNQMP_ZC1751_XM016_DC2=y
+CONFIG_SECURE_IOU=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_ZYNQ_SPI=y
--- /dev/null
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM015 DC1
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
+#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
+
+#define CONFIG_ZYNQ_GEM3
+#define CONFIG_ZYNQ_GEM_PHY_ADDR3 -1
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_AHCI
+
+#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
--- /dev/null
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM016 DC2
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
+#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
+
+#define CONFIG_ZYNQ_GEM2
+#define CONFIG_ZYNQ_GEM_PHY_ADDR2 -1
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_AHCI
+
+#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
projects / thirdparty / u-boot.git / commitdiff
