some other performance-oriented fixes to integrate

svn:r18395

diff --git a/doc/design-paper/performance.tex b/doc/design-paper/performance.tex
index 3c44d1d87bfb957bb69fe58599f02a386d8d99c0..43ce30543bea21ae40b9752fa0743677220056bf 100644 (file)
--- a/doc/design-paper/performance.tex
+++ b/doc/design-paper/performance.tex
@@ -51,7 +51,7 @@
  
 \maketitle
 
-\section{Minimzing latency of paths}
+\section{Minimizing latency of paths}
 
 Currently Tor selects paths purely by the random selection of nodes, biased by node bandwidth.
 This will sometimes cause high latency circuits due to multiple ocean crossings or otherwise congested links.
@@ -210,3 +210,14 @@ The exception is a padding cell, which has no circuit ID and a zero length paylo
 
 \end{document}
 
+Other items to add in somewhere:
+
+UDP transport
+
+Mike and Fallon's proposal
+
+Csaba's proposal to shrink the maximum circuit window.
+
+If extending a circuit fails, try extending a few other places before
+abandoning the circuit.
+