usb: dwc3: core: update LC timer as per USB Spec V3.2

[ Upstream commit 9149c9b0c7e046273141e41eebd8a517416144ac ]

This fix addresses STAR 9001285599, which only affects DWC_usb3 version
3.20a. The timer value for PM_LC_TIMER in DWC_usb3 3.20a for the Link
ECN changes is incorrect. If the PM TIMER ECN is enabled via GUCTL2[19],
the link compliance test (TD7.21) may fail. If the ECN is not enabled
(GUCTL2[19] = 0), the controller will use the old timer value (5us),
which is still acceptable for the link compliance test. Therefore, clear
GUCTL2[19] to pass the USB link compliance test: TD 7.21.

Cc: stable@vger.kernel.org
Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20240829094502.26502-1-quic_faisalh@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 82db59304492a9b02b7da9dab60f9d720643061c..b0ce9c1ed4501a93dad3f1eeb02f2271976d1726 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1054,6 +1054,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
                dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
        }
 
+       /*
+        * STAR 9001285599: This issue affects DWC_usb3 version 3.20a
+        * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
+        * link compliance test (TD7.21) may fail. If the ECN is not
+        * enabled (GUCTL2[19] = 0), the controller will use the old timer
+        * value (5us), which is still acceptable for the link compliance
+        * test. Therefore, do not enable PM TIMER ECM in 3.20a by
+        * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
+        */
+       if (DWC3_VER_IS(DWC3, 320A)) {
+               reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
+               reg &= ~DWC3_GUCTL2_LC_TIMER;
+               dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
+       }
+
        /*
         * When configured in HOST mode, after issuing U3/L2 exit controller
         * fails to send proper CRC checksum in CRC5 feild. Because of this

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index dbfb17ee4cca8a83f4b7b304c63547fa2120e40e..1765e58089fce73d084b126efd9e97b7d7ba382c 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -381,6 +381,7 @@
 
 /* Global User Control Register 2 */
 #define DWC3_GUCTL2_RST_ACTBITLATER            BIT(14)
+#define DWC3_GUCTL2_LC_TIMER                   BIT(19)
 
 /* Global User Control Register 3 */
 #define DWC3_GUCTL3_SPLITDISABLE               BIT(14)
@@ -1166,6 +1167,7 @@ struct dwc3 {
 #define DWC3_REVISION_290A     0x5533290a
 #define DWC3_REVISION_300A     0x5533300a
 #define DWC3_REVISION_310A     0x5533310a
+#define DWC3_REVISION_320A     0x5533320a
 #define DWC3_REVISION_330A     0x5533330a
 
 #define DWC31_REVISION_ANY     0x0