hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1);
}
break;
+ case EC_INSNABORT: {
+ uint32_t set = (syndrome >> 12) & 3;
+ bool fnv = (syndrome >> 10) & 1;
+ bool ea = (syndrome >> 9) & 1;
+ bool s1ptw = (syndrome >> 7) & 1;
+ uint32_t ifsc = (syndrome >> 0) & 0x3f;
+
+ trace_hvf_insn_abort(env->pc, set, fnv, ea, s1ptw, ifsc);
+
+ /* fall through */
+ }
default:
cpu_synchronize_state(cpu);
trace_hvf_exit(syndrome, ec, env->pc);
hvf_inject_fiq(void) "injecting FIQ"
hvf_inject_irq(void) "injecting IRQ"
hvf_data_abort(uint64_t va, uint64_t pa, bool isv, bool iswrite, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]"
+hvf_insn_abort(uint64_t pc, uint32_t set, bool fnv, bool ea, bool s1ptw, uint32_t ifsc) "insn abort: [pc=0x%"PRIx64" set=%d fnv=%d ea=%d s1ptw=%d ifsc=%d]"
hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%016"PRIx64
hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0x%016"PRIx64")"
hvf_unknown_hvc(uint64_t pc, uint64_t x0) "pc=0x%"PRIx64" unknown HVC! 0x%016"PRIx64