clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP

Add DPU_BUS and CMUREF mux/div, wire their registers and parents,
and update CLKS_NR_TOP. These use the new IDs appended to the
bindings to avoid ABI changes.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-5-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 8571c225d09074cfd1c299879c1e6b4a7322520a..91736b15c4b4a0759419517f7b04dd0a8f38a289 100644 (file)
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -17,7 +17,7 @@
 #include "clk-pll.h"
 
 /* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
+#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
 
@@ -45,6 +45,7 @@
 #define PLL_CON3_PLL_SHARED3                           0x024c
 #define PLL_CON0_PLL_SHARED4                           0x0280
 #define PLL_CON3_PLL_SHARED4                           0x028c
+#define CLK_CON_MUX_CLKCMU_DPU_BUS                     0x1000
 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS                 0x1004
 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU                 0x1008
 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS                        0x100c
@@ -103,6 +104,8 @@
 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS                 0x10e0
 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS                 0x10e4
 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS                 0x10e8
+#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF                 0x10f0
+#define CLK_CON_MUX_MUX_CMU_CMUREF                     0x10f4
 #define CLK_CON_DIV_CLKCMU_APM_BUS                     0x1800
 #define CLK_CON_DIV_CLKCMU_AUD_CPU                     0x1804
 #define CLK_CON_DIV_CLKCMU_BUS0_BUS                    0x1808
@@ -162,6 +165,7 @@
 #define CLK_CON_DIV_CLKCMU_VRA_BUS                     0x18e0
 #define CLK_CON_DIV_DIV_CLKCMU_DPU                     0x18e8
 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT                 0x18ec
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF                 0x18f0
 #define CLK_CON_DIV_PLL_SHARED0_DIV2                   0x18f4
 #define CLK_CON_DIV_PLL_SHARED0_DIV3                   0x18f8
 #define CLK_CON_DIV_PLL_SHARED0_DIV4                   0x18fc
@@ -253,6 +257,7 @@ static const unsigned long top_clk_regs[] __initconst = {
        PLL_CON3_PLL_SHARED3,
        PLL_CON0_PLL_SHARED4,
        PLL_CON3_PLL_SHARED4,
+       CLK_CON_MUX_CLKCMU_DPU_BUS,
        CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
        CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
        CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
@@ -311,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = {
        CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
        CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
        CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
+       CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
+       CLK_CON_MUX_MUX_CMU_CMUREF,
        CLK_CON_DIV_CLKCMU_APM_BUS,
        CLK_CON_DIV_CLKCMU_AUD_CPU,
        CLK_CON_DIV_CLKCMU_BUS0_BUS,
@@ -370,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = {
        CLK_CON_DIV_CLKCMU_VRA_BUS,
        CLK_CON_DIV_DIV_CLKCMU_DPU,
        CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
+       CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
        CLK_CON_DIV_PLL_SHARED0_DIV2,
        CLK_CON_DIV_PLL_SHARED0_DIV3,
        CLK_CON_DIV_PLL_SHARED0_DIV4,
@@ -465,6 +473,8 @@ PNAME(mout_pll_shared3_p)           = { "oscclk", "fout_shared3_pll" };
 PNAME(mout_pll_shared4_p)              = { "oscclk", "fout_shared4_pll" };
 PNAME(mout_pll_mmc_p)                  = { "oscclk", "fout_mmc_pll" };
 PNAME(mout_pll_g3d_p)                  = { "oscclk", "fout_g3d_pll" };
+PNAME(mout_cmu_dpu_bus_p)              = { "dout_cmu_dpu",
+                                           "dout_cmu_dpu_alt" };
 PNAME(mout_cmu_apm_bus_p)              = { "dout_cmu_shared0_div2",
                                            "dout_cmu_shared2_div2" };
 PNAME(mout_cmu_aud_cpu_p)              = { "dout_cmu_shared0_div2",
@@ -679,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p)          = { "dout_cmu_shared0_div3",
                                            "dout_cmu_shared4_div2",
                                            "dout_cmu_shared0_div4",
                                            "dout_cmu_shared4_div3" };
+PNAME(mout_cmu_cmuref_p)               = { "oscclk",
+                                           "dout_cmu_clk_cmuref" };
+PNAME(mout_cmu_clk_cmuref_p)           = { "dout_cmu_shared0_div4",
+                                           "dout_cmu_shared1_div4",
+                                           "dout_cmu_shared2_div2",
+                                           "oscclk" };
 
 /*
  * Register name to clock name mangling strategy used in this file
@@ -709,6 +725,8 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
            PLL_CON0_PLL_MMC, 4, 1),
        MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
            PLL_CON0_PLL_G3D, 4, 1),
+       MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
+           mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
        MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
            mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
        MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
@@ -837,6 +855,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
            mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
        MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
            mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
+       MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
+           mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
+       MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
+           mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
 };
 
 static const struct samsung_div_clock top_div_clks[] __initconst = {
@@ -981,6 +1003,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
            CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
        DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
            CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
+       DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
+           CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
+       DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
+           CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
 };
 
 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {