drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3p

A recent bspec tuning guide update asks us to program
COMMON_SLICE_CHICKEN4[5] on Xe3 and Xe3p platforms.  Add this setting to
our LRC tuning RTP table so that the setting will become part of each
context's LRC.

Bspec: 72161, 55902
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260224235055.3038710-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 90b9017770ea21d9990ebbd301fb4d6b617699d4..66ddad767ad442116a3c7fa94a9bd52382c95c00 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -176,6 +176,7 @@
 #define COMMON_SLICE_CHICKEN4                  XE_REG(0x7300, XE_REG_OPTION_MASKED)
 #define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE  REG_BIT(12)
 #define   DISABLE_TDC_LOAD_BALANCING_CALC      REG_BIT(6)
+#define   HW_FILTERING                         REG_BIT(5)
 
 #define COMMON_SLICE_CHICKEN3                          XE_REG(0x7304, XE_REG_OPTION_MASKED)
 #define XEHP_COMMON_SLICE_CHICKEN3                     XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index ea90e8c9975488dc191aca87047e79bac86346f1..f8de6a4bf1897b13dd7e100ca1fae7773e50a169 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -127,6 +127,11 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
 };
 
 static const struct xe_rtp_entry_sr lrc_tunings[] = {
+       { XE_RTP_NAME("Tuning: Windower HW Filtering"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, HW_FILTERING))
+       },
+
        /* DG2 */
 
        { XE_RTP_NAME("Tuning: L3 cache"),