can: rcar_can: BCR bitfield conversion

Convert CAN Bit Configuration Register field accesses to use the
FIELD_PREP() bitfield access macro.  While at it, fix the misspelling of
BRP.

This gets rid of custom function-like field preparation macros.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/01cfaedba2be22515ba8700893ea7f113df959c0.1755857536.git.geert+renesas@glider.be
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index 6f28dc9354511120571f36d35eb1e9f7df3ec78f..4c5c1f0446913d37d078e125ecda7c287e72ae5c 100644 (file)
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -152,10 +152,10 @@ static const struct can_bittiming_const rcar_can_bittiming_const = {
 #define RCAR_CAN_N_RX_MKREGS2  8
 
 /* Bit Configuration Register settings */
-#define RCAR_CAN_BCR_TSEG1(x)  (((x) & 0x0f) << 20)
-#define RCAR_CAN_BCR_BPR(x)    (((x) & 0x3ff) << 8)
-#define RCAR_CAN_BCR_SJW(x)    (((x) & 0x3) << 4)
-#define RCAR_CAN_BCR_TSEG2(x)  ((x) & 0x07)
+#define RCAR_CAN_BCR_TSEG1     GENMASK(23, 20)
+#define RCAR_CAN_BCR_BRP       GENMASK(17, 8)
+#define RCAR_CAN_BCR_SJW       GENMASK(5, 4)
+#define RCAR_CAN_BCR_TSEG2     GENMASK(2, 0)
 
 /* Mailbox and Mask Registers bits */
 #define RCAR_CAN_IDE           BIT(31)         /* ID Extension */
@@ -428,9 +428,10 @@ static void rcar_can_set_bittiming(struct net_device *ndev)
        struct can_bittiming *bt = &priv->can.bittiming;
        u32 bcr;
 
-       bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |
-             RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |
-             RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);
+       bcr = FIELD_PREP(RCAR_CAN_BCR_TSEG1, bt->phase_seg1 + bt->prop_seg - 1) |
+             FIELD_PREP(RCAR_CAN_BCR_BRP, bt->brp - 1) |
+             FIELD_PREP(RCAR_CAN_BCR_SJW, bt->sjw - 1) |
+             FIELD_PREP(RCAR_CAN_BCR_TSEG2, bt->phase_seg2 - 1);
        /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
         * All the registers are big-endian but they get byte-swapped on 32-bit
         * read/write (but not on 8-bit, contrary to the manuals)...