7.1-stable patches

added patches:
	arm64-cputype-add-c1-premium-definitions.patch
	arm64-cputype-add-c1-ultra-definitions.patch

diff --git a/queue-7.1/arm64-cputype-add-c1-premium-definitions.patch b/queue-7.1/arm64-cputype-add-c1-premium-definitions.patch
new file mode 100644 (file)
index 0000000..28cc17c
--- /dev/null
+++ b/queue-7.1/arm64-cputype-add-c1-premium-definitions.patch
@@ -0,0 +1,45 @@
+From d28413bfc5a255957241f1df5d7fd0c2cd74fe18 Mon Sep 17 00:00:00 2001
+From: Mark Rutland <mark.rutland@arm.com>
+Date: Tue, 9 Jun 2026 11:12:02 +0100
+Subject: arm64: cputype: Add C1-Premium definitions
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+commit d28413bfc5a255957241f1df5d7fd0c2cd74fe18 upstream.
+
+Add cputype definitions for C1-Premium. These will be used for errata
+detection in subsequent patches.
+
+These values can be found in the C1-Premium TRM:
+
+  https://developer.arm.com/documentation/109416/0100/
+
+... in section A.5.1 ("MIDR_EL1, Main ID Register").
+
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Will Deacon <will@kernel.org>
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/cputype.h |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/include/asm/cputype.h
++++ b/arch/arm64/include/asm/cputype.h
+@@ -100,6 +100,7 @@
+ #define ARM_CPU_PART_C1_ULTRA         0xD8C
+ #define ARM_CPU_PART_NEOVERSE_N3      0xD8E
+ #define ARM_CPU_PART_C1_PRO           0xD8B
++#define ARM_CPU_PART_C1_PREMIUM               0xD90
+ 
+ #define APM_CPU_PART_XGENE            0x000
+ #define APM_CPU_VAR_POTENZA           0x00
+@@ -193,6 +194,7 @@
+ #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
+ #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
+ #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
++#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
+ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
+ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+ #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

diff --git a/queue-7.1/arm64-cputype-add-c1-ultra-definitions.patch b/queue-7.1/arm64-cputype-add-c1-ultra-definitions.patch
new file mode 100644 (file)
index 0000000..a39a081
--- /dev/null
+++ b/queue-7.1/arm64-cputype-add-c1-ultra-definitions.patch
@@ -0,0 +1,45 @@
+From 60349e64a6c65f9f0aa118af711b3c7e137f07ff Mon Sep 17 00:00:00 2001
+From: Mark Rutland <mark.rutland@arm.com>
+Date: Tue, 9 Jun 2026 11:12:01 +0100
+Subject: arm64: cputype: Add C1-Ultra definitions
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+commit 60349e64a6c65f9f0aa118af711b3c7e137f07ff upstream.
+
+Add cputype definitions for C1-Ultra. These will be used for errata
+detection in subsequent patches.
+
+These values can be found in the C1-Ultra TRM:
+
+  https://developer.arm.com/documentation/108014/0100/
+
+... in section A.5.1 ("MIDR_EL1, Main ID Register").
+
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Will Deacon <will@kernel.org>
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/cputype.h |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/include/asm/cputype.h
++++ b/arch/arm64/include/asm/cputype.h
+@@ -97,6 +97,7 @@
+ #define ARM_CPU_PART_CORTEX_X925      0xD85
+ #define ARM_CPU_PART_CORTEX_A725      0xD87
+ #define ARM_CPU_PART_CORTEX_A720AE    0xD89
++#define ARM_CPU_PART_C1_ULTRA         0xD8C
+ #define ARM_CPU_PART_NEOVERSE_N3      0xD8E
+ #define ARM_CPU_PART_C1_PRO           0xD8B
+ 
+@@ -189,6 +190,7 @@
+ #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
+ #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+ #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
++#define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
+ #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
+ #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
+ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

diff --git a/queue-7.1/series b/queue-7.1/series
index a99e2ae37961789320ae7394d5e209dc4ca1cbe5..32070d3cb5e7c58f739b3eca6b0f726db39bc2eb 100644 (file)
--- a/queue-7.1/series
+++ b/queue-7.1/series
@@ -1,3 +1,5 @@
 fs-fcntl-fix-softirq-unsafe-lock-order-in-fasync-signaling.patch
 driver-core-faux-fix-root-device-registration.patch
 driver-core-reject-devices-with-unregistered-buses.patch
+arm64-cputype-add-c1-ultra-definitions.patch
+arm64-cputype-add-c1-premium-definitions.patch