platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write

The memory write feature supports 32-bit writes to any TPMI offset.
However, future hardware generations may not allow writes to non-32-bit
aligned addresses due to hardware optimizations.

Since all TPMI addresses are 64-bit aligned and correspond to 64-bit
registers, enforce 32-bit alignment for write operations.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://patch.msgid.link/20260326182446.3478672-1-srinivas.pandruvada@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

diff --git a/drivers/platform/x86/intel/vsec_tpmi.c b/drivers/platform/x86/intel/vsec_tpmi.c
index 9dddf4e5863e5e3aa829ed4798006e5b64f9048e..7fc6ff8d10406318a42e1fd1db1ac7777072824f 100644 (file)
--- a/drivers/platform/x86/intel/vsec_tpmi.c
+++ b/drivers/platform/x86/intel/vsec_tpmi.c
@@ -46,6 +46,7 @@
  * provided by the Intel VSEC driver.
  */
 
+#include <linux/align.h>
 #include <linux/auxiliary_bus.h>
 #include <linux/bitfield.h>
 #include <linux/debugfs.h>
@@ -479,6 +480,9 @@ static ssize_t mem_write(struct file *file, const char __user *userbuf, size_t l
        addr = array[2];
        value = array[3];
 
+       if (!IS_ALIGNED(addr, sizeof(u32)))
+               return -EINVAL;
+
        if (punit >= pfs->pfs_header.num_entries) {
                ret = -EINVAL;
                goto exit_write;