net: gem: Do not initialize BDs again

BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.

This patch solves the problem with repeatable tftp transfers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 5596e8f0915eebf8375c7e3b54b5b7eddf76f353..10a537e848404a33cf0f30c0b77d72b8ef3fa0fd 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -142,6 +142,7 @@ struct zynq_gem_priv {
        u32 rxbd_current;
        u32 rx_first_buf;
        int phyaddr;
+       int init;
        struct phy_device *phydev;
        struct mii_dev *bus;
 };
@@ -306,44 +307,52 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
                        SUPPORTED_1000baseT_Half |
                        SUPPORTED_1000baseT_Full;
 
-       /* Disable all interrupts */
-       writel(0xFFFFFFFF, &regs->idr);
-
-       /* Disable the receiver & transmitter */
-       writel(0, &regs->nwctrl);
-       writel(0, &regs->txsr);
-       writel(0, &regs->rxsr);
-       writel(0, &regs->phymntnc);
-
-       /* Clear the Hash registers for the mac address pointed by AddressPtr */
-       writel(0x0, &regs->hashl);
-       /* Write bits [63:32] in TOP */
-       writel(0x0, &regs->hashh);
+       if (!priv->init) {
+               /* Disable all interrupts */
+               writel(0xFFFFFFFF, &regs->idr);
+
+               /* Disable the receiver & transmitter */
+               writel(0, &regs->nwctrl);
+               writel(0, &regs->txsr);
+               writel(0, &regs->rxsr);
+               writel(0, &regs->phymntnc);
+
+               /*
+                * Clear the Hash registers for the mac address
+                * pointed by AddressPtr
+                */
+               writel(0x0, &regs->hashl);
+               /* Write bits [63:32] in TOP */
+               writel(0x0, &regs->hashh);
+
+               /* Clear all counters */
+               for (i = 0; i <= stat_size; i++)
+                       readl(&regs->stat[i]);
+
+               /* Setup RxBD space */
+               memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
+               /* Create the RxBD ring */
+               memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+
+               for (i = 0; i < RX_BUF; i++) {
+                       priv->rx_bd[i].status = 0xF0000000;
+                       priv->rx_bd[i].addr =
+                                       (u32)((char *) &(priv->rxbuffers) +
+                                                       (i * PKTSIZE_ALIGN));
+               }
+               /* WRAP bit to last BD */
+               priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
+               /* Write RxBDs to IP */
+               writel((u32) &(priv->rx_bd), &regs->rxqbase);
 
-       /* Clear all counters */
-       for (i = 0; i <= stat_size; i++)
-               readl(&regs->stat[i]);
+               /* Setup for DMA Configuration register */
+               writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 
-       /* Setup RxBD space */
-       memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
-       /* Create the RxBD ring */
-       memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+               /* Setup for Network Control register, MDIO, Rx and Tx enable */
+               setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 
-       for (i = 0; i < RX_BUF; i++) {
-               priv->rx_bd[i].status = 0xF0000000;
-               priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) +
-                                                       (i * PKTSIZE_ALIGN));
+               priv->init++;
        }
-       /* WRAP bit to last BD */
-       priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
-       /* Write RxBDs to IP */
-       writel((u32) &(priv->rx_bd), &regs->rxqbase);
-
-       /* Setup for DMA Configuration register */
-       writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
-
-       /* Setup for Network Control register, MDIO, Rx and Tx enable */
-       setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK );
 
        phy_detection(dev);