PLATFORM_RELFLAGS += -fno-strict-aliasing
# Xilinx, added to prevent unaligned accesses which started happening # with GCC 4.5.2 tools
PLATFORM_RELFLAGS += -mno-unaligned-access
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/xilinx/common
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
#define CONFIG_PHY_ADDR 7
-#define CONFIG_ZYNQ_GEM_OLD
-#define CONFIG_XGMAC_PHY_ADDR CONFIG_PHY_ADDR
-#define CONFIG_SYS_ENET
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MMC
#if defined(CONFIG_ZC770_XM010)
# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_GEM0
# define CONFIG_PHY_ADDR 7
-
-#define CONFIG_ZYNQ_GEM_OLD
-#define CONFIG_XGMAC_PHY_ADDR CONFIG_PHY_ADDR
-#define CONFIG_SYS_ENET
-
# define CONFIG_MMC
# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM013)
# define CONFIG_ZYNQ_SERIAL_UART0
-# define CONFIG_PHY_ADDR 7
-
-#define CONFIG_ZYNQ_GEM_OLD
-#define CONFIG_XGMAC_PHY_ADDR CONFIG_PHY_ADDR
-#define CONFIG_SYS_ENET
-
+# define CONFIG_ZYNQ_GEM1
+# define CONFIG_PHY_ADDR 7
# define CONFIG_ZYNQ_SPI
#else
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
#define CONFIG_PHY_ADDR 0
-#define CONFIG_ZYNQ_GEM_OLD
-#define CONFIG_XGMAC_PHY_ADDR CONFIG_PHY_ADDR
-#define CONFIG_SYS_ENET
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MMC