Xilinx: ARM: update uart clock input for ZC770/DC1GEM testing

The 100 Mb mode needs a 25 MHz clock input so this was needed
for this testing.

diff --git a/board/xilinx/dfe/xparameters_zynq.h b/board/xilinx/dfe/xparameters_zynq.h
index 1f7eb091b31a3dfe80fdf39eb15c66b8662f6b41..fc81e8d8023daf6de33a6a8c7c677272aed2daef 100755 (executable)
--- a/board/xilinx/dfe/xparameters_zynq.h
+++ b/board/xilinx/dfe/xparameters_zynq.h
@@ -51,7 +51,8 @@
 #define XPAR_XUARTPSS_0_INTR           51
 #define XPAR_XUARTPSS_1_DEVICE_ID      1
 #define XPAR_XUARTPSS_1_BASEADDR       XPSS_UART1_BASEADDR
-#define XPAR_XUARTPSS_1_CLOCK_HZ       13756480
+#define XPAR_XUARTPSS_1_CLOCK_HZ_OLD   13756480
+#define XPAR_XUARTPSS_1_CLOCK_HZ       50000000
 #define XPAR_XUARTPSS_1_INTR           75
 #define XPAR_XUARTPSS_NUM_INSTANCES    2