arm64: dts: qcom: x1e80100: Add IRIS video codec

Add the IRIS video codec to accelerate video decoding/encoding. Copied
mostly from sm8550.dtsi, only the opp-table is slightly different for X1E.
For opp-240000000, we need to vote for a higher OPP on one of the power
domains, because the voltage requirements for the PLL and the derived
clocks differ (sm8550.dtsi has the same).

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # x1e Inspiron 14p
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on Thinkpad T14S OLED
Tested-by: Anthony Ruhier <aruhier@mailbox.org> # Lenovo Slim 7x
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-2-1f928de08fd4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index ba602eddfb54616ad38205570bc56a1f0e62c023..a6305077f150d59ef8fdbd13fe3ba03d43646c91 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5234,6 +5234,93 @@
                        };
                };
 
+               iris: video-codec@aa00000 {
+                       compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";
+
+                       reg = <0 0x0aa00000 0 0xf0000>;
+                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+                       power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                                       <&videocc VIDEO_CC_MVS0_GDSC>,
+                                       <&rpmhpd RPMHPD_MXC>,
+                                       <&rpmhpd RPMHPD_MMCX>;
+                       power-domain-names = "venus",
+                                            "vcodec0",
+                                            "mxc",
+                                            "mmcx";
+                       operating-points-v2 = <&iris_opp_table>;
+
+                       clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                                <&videocc VIDEO_CC_MVS0C_CLK>,
+                                <&videocc VIDEO_CC_MVS0_CLK>;
+                       clock-names = "iface",
+                                     "core",
+                                     "vcodec0_core";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "cpu-cfg",
+                                            "video-mem";
+
+                       memory-region = <&video_mem>;
+
+                       resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+                       reset-names = "bus";
+
+                       iommus = <&apps_smmu 0x1940 0>,
+                                <&apps_smmu 0x1947 0>;
+                       dma-coherent;
+
+                       /*
+                        * IRIS firmware is signed by vendors, only
+                        * enable on boards where the proper signed firmware
+                        * is available.
+                        */
+                       status = "disabled";
+
+                       iris_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-192000000 {
+                                       opp-hz = /bits/ 64 <192000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs_d1>,
+                                                       <&rpmhpd_opp_low_svs_d1>;
+                               };
+
+                               opp-240000000 {
+                                       opp-hz = /bits/ 64 <240000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-338000000 {
+                                       opp-hz = /bits/ 64 <338000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-366000000 {
+                                       opp-hz = /bits/ 64 <366000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>,
+                                                       <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-444000000 {
+                                       opp-hz = /bits/ 64 <444000000>;
+                                       required-opps = <&rpmhpd_opp_nom>,
+                                                       <&rpmhpd_opp_nom>;
+                               };
+
+                               opp-481000000 {
+                                       opp-hz = /bits/ 64 <481000000>;
+                                       required-opps = <&rpmhpd_opp_turbo>,
+                                                       <&rpmhpd_opp_turbo>;
+                               };
+                       };
+               };
+
                videocc: clock-controller@aaf0000 {
                        compatible = "qcom,x1e80100-videocc";
                        reg = <0 0x0aaf0000 0 0x10000>;