return display->vlv_clock.hpll_freq;
}
-static int vlv_get_cck_clock(struct drm_device *drm,
+static int vlv_clock_get_cck(struct drm_device *drm,
const char *name, u32 reg, int ref_freq)
{
u32 val;
int vlv_clock_get_hrawclk(struct drm_device *drm)
{
/* RAWCLK_FREQ_VLV register updated from power well code */
- return vlv_get_cck_clock(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL,
+ return vlv_clock_get_cck(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
struct intel_display *display = to_intel_display(drm);
if (!display->vlv_clock.czclk_freq) {
- display->vlv_clock.czclk_freq = vlv_get_cck_clock(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
+ display->vlv_clock.czclk_freq = vlv_clock_get_cck(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
}
int vlv_clock_get_cdclk(struct drm_device *drm)
{
- return vlv_get_cck_clock(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
+ return vlv_clock_get_cck(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
int vlv_clock_get_gpll(struct drm_device *drm)
{
- return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
+ return vlv_clock_get_cck(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
vlv_clock_get_czclk(drm));
}