clk: si5341: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>

diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 5004888c7eca5f85a444ec6de684b8dd79635622..2499b771cd83e313eafd83cb0519b1b94da73a61 100644 (file)
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -663,8 +663,8 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
        return f;
 }
 
-static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *parent_rate)
+static int si5341_synth_clk_determine_rate(struct clk_hw *hw,
+                                          struct clk_rate_request *req)
 {
        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
        u64 f;
@@ -672,15 +672,21 @@ static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
        /* The synthesizer accuracy is such that anything in range will work */
        f = synth->data->freq_vco;
        do_div(f, SI5341_SYNTH_N_MAX);
-       if (rate < f)
-               return f;
+       if (req->rate < f) {
+               req->rate = f;
+
+               return 0;
+       }
 
        f = synth->data->freq_vco;
        do_div(f, SI5341_SYNTH_N_MIN);
-       if (rate > f)
-               return f;
+       if (req->rate > f) {
+               req->rate = f;
 
-       return rate;
+               return 0;
+       }
+
+       return 0;
 }
 
 static int si5341_synth_program(struct clk_si5341_synth *synth,
@@ -741,7 +747,7 @@ static const struct clk_ops si5341_synth_clk_ops = {
        .prepare = si5341_synth_clk_prepare,
        .unprepare = si5341_synth_clk_unprepare,
        .recalc_rate = si5341_synth_clk_recalc_rate,
-       .round_rate = si5341_synth_clk_round_rate,
+       .determine_rate = si5341_synth_clk_determine_rate,
        .set_rate = si5341_synth_clk_set_rate,
 };