spi: atmel: Add support for handling GCLK as a clock source

The SPI peripheral clock is typically used to derive the serial
clock (SPCK) via the FLEX_SPI_CSRx.SCBR field. However, on platforms
like the SAM9X7 SoC, where the peripheral clock can reach up to 266 MHz,
this may exceed the SCBR limit, causing SPI transfers to fail.
This patch adds support for using the SPI Generic Clock (GCLK) as an
alternative and more flexible clock source for SPCK generation.
The FLEX_SPI_MR.BRSRCCLK bit is updated accordingly to select between the
peripheral clock and GCLK.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Link: https://patch.msgid.link/20250730101015.323964-3-manikandan.m@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 409f544d898375c802c7ded97a57d02ed332991d..89977bff76d2706f27ba5d2562cbaf937d5744db 100644 (file)
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -256,6 +256,7 @@ struct atmel_spi {
        void __iomem            *regs;
        int                     irq;
        struct clk              *clk;
+       struct clk              *gclk;
        struct platform_device  *pdev;
        unsigned long           spi_clk;
 
@@ -1480,6 +1481,8 @@ static void atmel_get_caps(struct atmel_spi *as)
 
 static void atmel_spi_init(struct atmel_spi *as)
 {
+       u32 mr = 0;
+
        spi_writel(as, CR, SPI_BIT(SWRST));
        spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 
@@ -1487,12 +1490,17 @@ static void atmel_spi_init(struct atmel_spi *as)
        if (as->fifo_size)
                spi_writel(as, CR, SPI_BIT(FIFOEN));
 
-       if (as->caps.has_wdrbt) {
-               spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
-                               | SPI_BIT(MSTR));
-       } else {
-               spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
-       }
+       /*
+        * If GCLK is selected as the source clock for the bit rate generation
+        * Enable the BRSRCCLK/FDIV/DIV32 bit
+        */
+       if (as->gclk)
+               mr |= SPI_BIT(FDIV);
+
+       if (as->caps.has_wdrbt)
+               mr |= SPI_BIT(WDRBT);
+
+       spi_writel(as, MR, mr | SPI_BIT(MODFDIS) | SPI_BIT(MSTR));
 
        if (as->use_pdc)
                spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
@@ -1555,6 +1563,11 @@ static int atmel_spi_probe(struct platform_device *pdev)
        as->phybase = regs->start;
        as->irq = irq;
        as->clk = clk;
+       as->gclk = devm_clk_get_optional(&pdev->dev, "spi_gclk");
+       if (IS_ERR(as->gclk)) {
+               ret = PTR_ERR(as->gclk);
+               goto out_unmap_regs;
+       }
 
        init_completion(&as->xfer_completion);
 
@@ -1615,7 +1628,19 @@ static int atmel_spi_probe(struct platform_device *pdev)
        if (ret)
                goto out_free_irq;
 
-       as->spi_clk = clk_get_rate(clk);
+       /*
+        * In cases where the peripheral clock is higher,the FLEX_SPI_CSRx.SCBR
+        * exceeds the threshold (SCBR ≤ 255), the GCLK is used as the source clock
+        * for the SPCK (SPI Serial Clock) bit rate generation
+        */
+       if (as->gclk) {
+               ret = clk_prepare_enable(as->gclk);
+               if (ret)
+                       goto out_disable_clk;
+               as->spi_clk = clk_get_rate(as->gclk);
+       } else {
+               as->spi_clk = clk_get_rate(clk);
+       }
 
        as->fifo_size = 0;
        if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
@@ -1650,6 +1675,8 @@ out_free_dma:
 
        spi_writel(as, CR, SPI_BIT(SWRST));
        spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
+       clk_disable_unprepare(as->gclk);
+out_disable_clk:
        clk_disable_unprepare(clk);
 out_free_irq:
 out_unmap_regs:
@@ -1685,6 +1712,8 @@ static void atmel_spi_remove(struct platform_device *pdev)
        spin_unlock_irq(&as->lock);
 
        clk_disable_unprepare(as->clk);
+       if (as->gclk)
+               clk_disable_unprepare(as->gclk);
 
        pm_runtime_put_noidle(&pdev->dev);
        pm_runtime_disable(&pdev->dev);
@@ -1696,6 +1725,8 @@ static int atmel_spi_runtime_suspend(struct device *dev)
        struct atmel_spi *as = spi_controller_get_devdata(host);
 
        clk_disable_unprepare(as->clk);
+       if (as->gclk)
+               clk_disable_unprepare(as->gclk);
        pinctrl_pm_select_sleep_state(dev);
 
        return 0;
@@ -1705,10 +1736,20 @@ static int atmel_spi_runtime_resume(struct device *dev)
 {
        struct spi_controller *host = dev_get_drvdata(dev);
        struct atmel_spi *as = spi_controller_get_devdata(host);
+       int ret;
 
        pinctrl_pm_select_default_state(dev);
 
-       return clk_prepare_enable(as->clk);
+       ret = clk_prepare_enable(as->clk);
+       if (ret)
+               return ret;
+       if (as->gclk) {
+               ret = clk_prepare_enable(as->gclk);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
 }
 
 static int atmel_spi_suspend(struct device *dev)
@@ -1736,10 +1777,17 @@ static int atmel_spi_resume(struct device *dev)
        ret = clk_prepare_enable(as->clk);
        if (ret)
                return ret;
+       if (as->gclk) {
+               ret = clk_prepare_enable(as->gclk);
+               if (ret)
+                       return ret;
+       }
 
        atmel_spi_init(as);
 
        clk_disable_unprepare(as->clk);
+       if (as->gclk)
+               clk_disable_unprepare(as->gclk);
 
        if (!pm_runtime_suspended(dev)) {
                ret = atmel_spi_runtime_resume(dev);