riscv: Add support for alias names for cpus

Some cpus are known by multiple names or have their name changed after
support has already been added to GCC.  Add support to the riscv port
that allows setting up alternate names or aliases for a cpu's canonical
name.

2026-06-17  Peter Bergner  <bergner@tenstorrent.com>

gcc/
	* common/config/riscv/riscv-common.cc (struct riscv_cpu_alias_info):
	New struct.
	(riscv_cpu_alias_table): New.
	(riscv_find_cpu): Add support for cpu alias names.
	(riscv_get_valid_option_values): Likewise.
	Add an early loop exit if we found a duplicate name.
	* config/riscv/riscv-cores.def (RISCV_CORE_ALIAS): New macro.

Signed-off-by: Peter Bergner <bergner@tenstorrent.com>

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index ed5d6839e92e86e00470844c895c27dd7be31f3a..74929381a06b295d5b6c12e7246011c5961a2ef8 100644 (file)
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -279,6 +279,23 @@ static const riscv_profiles riscv_profiles_table[] =
     {NULL, NULL}
 };
 
+/* Alternate/alias name for a CPU we know about.  */
+struct riscv_cpu_alias_info {
+  /* This CPU's canonical name.  */
+  const char *name;
+
+  /* This CPU's alternate name.  */
+  const char *alias;
+};
+
+static const riscv_cpu_alias_info riscv_cpu_alias_table[] =
+{
+#define RISCV_CORE_ALIAS(CANONICAL_NAME, ALIAS_NAME) \
+    {CANONICAL_NAME, ALIAS_NAME},
+#include "../../../config/riscv/riscv-cores.def"
+    {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1699,6 +1716,14 @@ riscv_find_cpu (const char *cpu)
       if (strcmp (cpu, name) == 0)
        return cpu_info;
     }
+
+  /* We did not find CPU, check if CPU is a core's alias name and look it
+     up using its canonical name.  */
+  const riscv_cpu_alias_info *alias_info = &riscv_cpu_alias_table[0];
+  for (; alias_info->alias != NULL; alias_info++)
+    if (strcmp (cpu, alias_info->alias) == 0)
+      return riscv_find_cpu (alias_info->name);
+
   return NULL;
 }
 
@@ -2220,13 +2245,31 @@ riscv_get_valid_option_values (int option_code,
            int i;
            const char *str;
            FOR_EACH_VEC_ELT (v, i, str)
-             {
-               if (!strcmp (str, cpu_info->name))
+             if (!strcmp (str, cpu_info->name))
+               {
                  skip = true;
-             }
+                 break;
+               }
            if (!skip)
              v.safe_push (cpu_info->name);
          }
+
+       const riscv_cpu_alias_info *alias_info = &riscv_cpu_alias_table[0];
+       for (; alias_info->alias; alias_info++)
+         {
+           /* Skip duplicates.  */
+           bool skip = false;
+           int i;
+           const char *str;
+           FOR_EACH_VEC_ELT (v, i, str)
+             if (!strcmp (str, alias_info->alias))
+               {
+                 skip = true;
+                 break;
+               }
+           if (!skip)
+             v.safe_push (alias_info->alias);
+         }
       }
       break;
     case OPT_mcpu_:
@@ -2234,6 +2277,10 @@ riscv_get_valid_option_values (int option_code,
        const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0];
        for (;cpu_info->name; ++cpu_info)
          v.safe_push (cpu_info->name);
+
+       const riscv_cpu_alias_info *alias_info = &riscv_cpu_alias_table[0];
+       for (; alias_info->alias; alias_info++)
+         v.safe_push (alias_info->alias);
       }
       break;
     default:

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 4cfd924b47f01d7907c129ad7a47daec5eb35db0..9dd355c29a7dea263a72b610dbca6c0f31dcbf22 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -73,11 +73,23 @@ RISCV_TUNE("arc-v-rmx-100-series", arcv_rmx100, arcv_rmx100_tune_info)
    The ARCH is the default arch of the core, represented as a string,
    can be NULL if no default arch.
    The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.  */
+   will be made, represented as an identifier.
+
+   If the core has an alternate name(s), an alias(es) can be created to map
+   an alternate name to the core's canonical name.  Before using #include
+   to read this file, define a macro:
+
+      RISCV_CORE_ALIAS(CANONICAL_NAME, ALIAS_NAME)
+
+   CANONICAL_NAME is the normal name of the core, represented as a string.
+   ALIAS_NAME is the alternate name for the core, represented as a string.  */
 
 #ifndef RISCV_CORE
 #define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
 #endif
+#ifndef RISCV_CORE_ALIAS
+#define RISCV_CORE_ALIAS(CANONICAL_NAME, ALIAS_NAME)
+#endif
 
 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
@@ -209,3 +221,4 @@ RISCV_CORE("spacemit-x60",    "rv64imafdcv_zba_zbb_zbc_zbs_zicboz_zicond_"
                              "spacemit-x60")
 
 #undef RISCV_CORE
+#undef RISCV_CORE_ALIAS