x86/CPU/AMD: Add ZenX generations flags

[ Upstream commit 30fa92832f405d5ac9f263e99f62445fa3084008 ]

Add X86_FEATURE flags for each Zen generation. They should be used from
now on instead of checking f/m/s.

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lore.kernel.org/r/20231120104152.13740-2-bp@alien8.de
Stable-dep-of: c7b2edd8377b ("perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index bd33f6366c80d0c13d2a663a41fcff0d46dfc55b..1f9db287165acc19f2354bbfb50a53257b671465 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -218,7 +218,7 @@
 #define X86_FEATURE_IBRS               ( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB               ( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP              ( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN                        (7*32+28) /* "" CPU based on Zen microarchitecture */
+#define X86_FEATURE_ZEN                        ( 7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV                ( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED      ( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL  ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
@@ -312,6 +312,9 @@
 #define X86_FEATURE_SRSO_ALIAS         (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
 #define X86_FEATURE_IBPB_ON_VMEXIT     (11*32+26) /* "" Issue an IBPB only on VMEXIT */
 #define X86_FEATURE_APIC_MSRS_FENCE    (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
+#define X86_FEATURE_ZEN2               (11*32+28) /* "" CPU based on Zen2 microarchitecture */
+#define X86_FEATURE_ZEN3               (11*32+29) /* "" CPU based on Zen3 microarchitecture */
+#define X86_FEATURE_ZEN4               (11*32+30) /* "" CPU based on Zen4 microarchitecture */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI           (12*32+ 4) /* AVX VNNI instructions */

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 031bca974fbf3729ee6f1083f914bd1a022a1ffc..5391385707b3f598fd43624ecf68aa563861fd7a 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -620,6 +620,49 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
        }
 
        resctrl_cpu_detect(c);
+
+       /* Figure out Zen generations: */
+       switch (c->x86) {
+       case 0x17: {
+               switch (c->x86_model) {
+               case 0x00 ... 0x2f:
+               case 0x50 ... 0x5f:
+                       setup_force_cpu_cap(X86_FEATURE_ZEN);
+                       break;
+               case 0x30 ... 0x4f:
+               case 0x60 ... 0x7f:
+               case 0x90 ... 0x91:
+               case 0xa0 ... 0xaf:
+                       setup_force_cpu_cap(X86_FEATURE_ZEN2);
+                       break;
+               default:
+                       goto warn;
+               }
+               break;
+       }
+       case 0x19: {
+               switch (c->x86_model) {
+               case 0x00 ... 0x0f:
+               case 0x20 ... 0x5f:
+                       setup_force_cpu_cap(X86_FEATURE_ZEN3);
+                       break;
+               case 0x10 ... 0x1f:
+               case 0x60 ... 0xaf:
+                       setup_force_cpu_cap(X86_FEATURE_ZEN4);
+                       break;
+               default:
+                       goto warn;
+               }
+               break;
+       }
+       default:
+               break;
+       }
+
+       return;
+
+warn:
+       WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
 }
 
 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
@@ -978,8 +1021,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
 
 static void init_amd_zn(struct cpuinfo_x86 *c)
 {
-       set_cpu_cap(c, X86_FEATURE_ZEN);
-
 #ifdef CONFIG_NUMA
        node_reclaim_distance = 32;
 #endif
@@ -1042,6 +1083,22 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
        }
 }
 
+static void init_amd_zen(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen2(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen3(struct cpuinfo_x86 *c)
+{
+}
+
+static void init_amd_zen4(struct cpuinfo_x86 *c)
+{
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
        early_init_amd(c);
@@ -1080,6 +1137,15 @@ static void init_amd(struct cpuinfo_x86 *c)
        case 0x19: init_amd_zn(c); break;
        }
 
+       if (boot_cpu_has(X86_FEATURE_ZEN))
+               init_amd_zen(c);
+       else if (boot_cpu_has(X86_FEATURE_ZEN2))
+               init_amd_zen2(c);
+       else if (boot_cpu_has(X86_FEATURE_ZEN3))
+               init_amd_zen3(c);
+       else if (boot_cpu_has(X86_FEATURE_ZEN4))
+               init_amd_zen4(c);
+
        /*
         * Enable workaround for FXSAVE leak on CPUs
         * without a XSaveErPtr feature